Pin Configuration (Top View) - NEC V850E/IA1 mPD703116 User Manual

1.5 Pin Configuration (Top View)

• • • • 144-pin plastic LQFP (fine pitch) (20 × × × × 20)
µ µ µ µ PD703116GJ-×××
×××-UEN, 703116GJ(A)-××× ××× ×××
µ µ µ µ PD70F3116GJ-UEN, 70F3116GJ(A)-UEN, 70F3116GJ(A1)-UEN
ANI07 1
AV 2
DD
AV 3
SS
AV 4
REF1
ANI10 5
ANI11 6
ANI12 7
ANI13 8
ANI14 9
ANI15 10
ANI16 11
ANI17 12
TRIG _ DBG
13
AD3 _ DBG
14
AD2 _ DBG
15
AD1 _ DBG
Note 1 16
AD0 _ DBG
17
SYNC 18
CLK _ DBG
19
RESET 20
CV 21
DD
CV 22
SS
X1 23
X2 24
CKSEL 25
MODE0 26
MODE1 27
MODE2 28
SI0/P40 29
SO0/P41 30
SCK0/P42 31
SI1/P43 32
SO1/P44 33
SCK1/P45 34
CRXD/P46 35
CTXD/P47 36
On-chip in µ PD70F3116 only.
Notes 1.
µ PD703116 is as follows.
TRIG_DBG: IC1, AD0_DBG to AD3_DBG: IC2, SYNC: IC3, CLK_DBG: IC4
µ PD703116: IC5
2.
µ PD70F3116: V
Cautions 1. When using the µ µ µ µ PD70F3116 in normal mode, connect the V
2. When using the µ µ µ µ PD703116, the processing when the IC1 to IC5 pins are unused is as
follows.
IC1 to IC4 pins: Leave open.
IC5 pin: Independently connect to V
CHAPTER 1 INTRODUCTION
×××-UEN, 703116GJ(A1)-××× ××× ×××
PP
SS5
User's Manual U14492EJ3V0UD
××× ×××-UEN ×××
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
pin to V
PP
via a resistor.
TIUD11/TO11/P13
TCLR10/INTP101/P12
TCUD10/INTP100/P11
TIUD10/TO10/P10
PCM4
HLDRQ/PCM3
HLDAK/PCM2
CLKOUT/PCM1
WAIT/PCM0
PCT7
ASTB/PCT6
PCT5
RD/PCT4
PCT3
PCT2
UWR/PCT1
LWR/PCT0
V
DD5
V
SS5
Note 2
CS7/PCS7
CS6/PCS6
CS5/PCS5
CS4/PCS4
CS3/PCS3
CS2/PCS2
CS1/PCS1
CS0/PCS0
A23/PDH7
A22/PDH6
A21/PDH5
A20/PDH4
A19/PDH3
A18/PDH2
A17/PDH1
A16/PDH0
.
SS5
35