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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
9.5.6 Application example
(1) Interval timer
This section explains an example in which timer 4 is used as an interval timer with 16-bit precision.
Interrupt requests (INTCM4) are output at equal intervals (refer to Figure 9-98 TM4 Compare Operation
Example). The setup procedure is shown below.
<1> Set (1) the TM4CAE0 bit.
<2> Set each register.
• Select the count clock using the CS2 to CS0 bits of the TMC4 register.
• Set the compare value in the CM4 register.
<3> Start counting by setting (1) the TM4CE0 bit.
<4> If the TM4 register and CM4 register values match, an INTCM4 interrupt is generated.
<5> INTCM4 interrupts are generated thereafter at equal intervals.
9.5.7 Precautions
Various precautions concerning timer 4 are shown below.
(1) To operate TM4, first set (1) the TM4CAE0 bit of the TMC4 register.
(2) Up to 4 clocks are required after a value is set in the TM4CE0 bit of the TMC4 register until the set value is
transferred to internal units. When a count operation begins, the count cycle from 0000H to 0001H differs
from subsequent count cycles.
(3) To initialize the TM4 register status and start counting again, clear (0) the TM4CE0 bit and then set (1) the
TM4CE0 bit after an interval of 4 clocks has elapsed.
(4) Up to 4 clocks are required until the value that was set in the CM4 register is transferred to internal units.
When writing continuously to the CM4 register, be sure to secure a time interval of at least 4 clocks.
(5) The CM4 register can be overwritten only once during a timer/counter operation (from 0000H until an
INTCM4 interrupt is generated due to a match of the TM4 register and CM4 register). If this cannot be
secured by the application, make sure that the CM4 register is not overwritten during a timer/counter
operation.
(6) The count clock must not be changed during a timer operation. If it is to be overwritten, it should be
overwritten after the TM4CE0 bit is cleared (0). If the count clock is overwritten during a timer operation,
operation cannot be guaranteed.
(7) An INTCM4 interrupt will be generated after an overflow if a value less than the counter value is written in the
CM4 register during TM4 register operation.
User's Manual U14492EJ3V0UD
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