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11.14.2 Burst read mode
Burst read mode is implemented in the FCAN to enable faster access to complete messages and secure the
synchrony of data.
Burst read mode starts up automatically each time the CPU reads the M_DLCn register and data is then copied
from the message buffer area to a temporary read buffer.
Data continues to be read from the temporary buffer as long as the CPU keeps directly incrementing (+1) the read
address (when data is read in the following order: M_DLCn register → M_CTRLn register → M_TIMEn register →
M_DATAn0 to M_DATAn7 registers → M_IDLn, M_IDHn register).
If these linear address rules are not followed or if access is attempted to an address that is lower than the M_IDHn
register's address (such as the M_CONFn register or M_STATn register), burst read mode becomes invalid.
Caution 16-bit read access is required for the memory buffer area when using the burst read mode.
If 8-bit access (byte read operation) is attempted, burst read mode does not start up even if the
address is linearly incremented (+1) as described above.
Remark
n = 00 to 31
CHAPTER 11 FCAN CONTROLLER
User's Manual U14492EJ3V0UD
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