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4.4 Bus Cycle Type Control Function
In the V850E/IA1, the following external devices can be connected directly to each memory block.
• SRAM, external ROM, external I/O
Connected external devices are specified by bus cycle type configuration registers 0, 1 (BCT0, BCT1).
(1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
These registers can be read/written in 16-bit units.
Caution Write to the BCT0 and BCT1 registers after reset, and then do not change the set values.
Also, do not access an external memory area other than the one for this initialization
routine until the initial setting of the BCT0 and BCT1 registers is complete. However, it is
possible to access external memory areas whose initial settings are complete.
15
14
13
BCT0
ME3
1
0
CSn signal
CS3
15
14
13
BCT1
ME7
1
0
CSn signal
CS7
Bit Position
Bit Name
15, 11, 7, 3
MEn
(BCT0),
(n = 0 to 7)
15, 11, 7, 3
(BCT1)
CHAPTER 4 BUS CONTROL FUNCTION
12
11
10
9
8
7
0
ME2
1
0
0
ME1
CS2
CS1
12
11
10
9
8
7
0
ME6
1
0
0
ME5
CS6
CS5
Sets memory controller operation enable for each chip select.
MEn
0
Operation disabled
1
Operation enabled
User's Manual U14492EJ3V0UD
6
5
4
3
2
1
1
0
0
ME0
1
0
CS0
6
5
4
3
2
1
1
0
0
ME4
1
0
CS4
Function
Memory Controller Operation Enable
0
Address
Initial value
0
FFFFF480H
CCCCH
0
Address
Initial value
0
FFFFF482H
CCCCH
115
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