Synchronous Mode - NEC V850E/IA1 mPD703116 User Manual

32-bit single-chip microcontrollers

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10.3.6 Synchronous mode

The synchronous mode can be set with the ASCKn pin, which is the serial clock I/O pin (n = 1, 2).

The synchronous mode is set with the MOD bit of the ASIMn1 register, and the serial clock to be used for

synchronization is selected with the SCLS bit of the ASIMn0 register.

In the synchronous mode, external clock input is selected when the value of the SCLS bit is 0 (default), and the

serial clock output is selected in the case of all other settings. Therefore, when performing settings, make sure that

outputs between connection nodes do not conflict.

In the synchronous mode, the falling edge of the serial clock is used as the transmission timing, and the rising edge

as the reception timing, but transmit data is output with a delay of 1 system clock (serial clock) (in the external clock

synchronous mode, the maximum delay is 2.5 system clocks).

Figure 10-20. Transmission/Reception Timing in Synchronous Mode

On the data output side, the data changes at the falling edge of the serial clock output.

On the data input side, the data is latched at the rising edge of the serial clock output.

Serial clock output continues as long as the setting is not canceled.

Remark n = 1, 2

CHAPTER 10 SERIAL INTERFACE FUNCTION

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