System Register Set - NEC V850E/IA1 mPD703116 User Manual

32-bit single-chip microcontrollers
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3.2.2

System register set

System registers control the status of the CPU and hold interrupt information.
To read/write these system registers, specify a system register number indicated below using the system register
load/store instruction (LDSR or STSR instruction).
No.
0
Status saving register during interrupt (EIPC)
1
Status saving register during interrupt (EIPSW)
2
Status saving register during NMI (FEPC)
3
Status saving register during NMI (FEPSW)
4
Interrupt source register (ECR)
5
Program status word (PSW)
6 to 15
Reserved number for future function expansion (operations that access
these register numbers cannot be guaranteed).
16
Status saving register during CALLT execution (CTPC)
17
Status saving register during CALLT execution (CTPSW)
18
Status saving register during exception/debug trap (DBPC)
19
Status saving register during exception/debug trap (DBPSW)
20
CALLT base pointer (CTBP)
21 to 31
Reserved number for future function expansion (operations that access
these register numbers cannot be guaranteed).
Notes 1.
Because this register has only one set, to allow multiple interrupts, it is necessary to save this register
by program.
2.
Access is only possible when the DBTRAP instruction is executed.
Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 with the LDSR instruction, bit 0 will be ignored
when the program is returned by the RETI instruction after interrupt servicing (because bit 0 of
the PC is fixed to 0). When setting the value of EIPC, FEPC, or CTPC, use an even value (bit 0 =
0).
Remark
: Access allowed
×: Access prohibited
(1) Interrupt source register (ECR)
31
ECR
Bit Position
Bit Name
31 to 16
FECC
15 to 0
EICC
CHAPTER 3 CPU FUNCTION
Table 3-2. System Register Numbers
System Register Name
Note 1
16 15
FECC
Exception code of non-maskable interrupt (NMI)
Exception code of exception/maskable interrupt
User's Manual U14492EJ3V0UD
Operand Specification
LDSR Instruction
×
×
Note 2
Note 2
×
0
EICC
Function
STSR Instruction
×
×
Initial value
00000000H
65

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