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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
9.4.7 Precautions
Various precautions concerning timer 3 are shown below.
(1) If a conflict occurs between the reading of the CC30 register and a capture operation when the CC30 register
is used in capture mode, an external trigger (INTP30) valid edge is detected and an external interrupt request
signal (INTCC30) is generated however, the timer value is not stored in the CC30 register.
(2) If a conflict occurs between the reading of the CC31 register and a capture operation when the CC31 register
is used in capture mode, an external trigger (INTP31) valid edge is detected and an external interrupt request
signal (INTCC31) is generated however, the timer value is not stored in the CC31 register.
(3) The following bits and registers must not be rewritten during operation (TMC30 register TM3CE = 1).
• CS2 to CS0 bits of TMC30 register
• TMC31 register
• SESC register
(4) The TM3CAE bit of the TMC30 register is a TM3 reset signal. To use TM3, first set (1) the TM3CAE bit.
(5) The analog noise elimination time + two cycles of the input clock are required to detect a valid edge of the
external interrupt input (INTP30 or INTP31) and external clock input (TI3). Therefore, edge detection will not
be performed normally for changes that are less than the analog noise elimination time + two cycles of the
input clock. For the analog noise elimination, refer to 14.4 Noise Eliminator.
(6) The operation of an external interrupt output (INTCC30 or INTCC31) is automatically determined according to
the operating state of the capture/compare registers 30, 31 (CC30, CC31). When the capture/compare
register is used for a capture mode, the external trigger (INTP30, INTP31) is used for valid edge detection.
When the capture/compare register is used for a compare mode, the external interrupt output is used for a
match interrupt indicating a match with the TM3 register.
(7) If the ENT1 and ALV bits of the TMC31 register are changed at the same time, a glitch (spike shaped noise)
may be generated in the TO3 pin output. Either create a circuit configuration that will not malfunction even if
a glitch is generated or make sure that the ENT1 and ALV bits do not change at the same time.
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User's Manual U14492EJ3V0UD
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