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8.3.5 Peripheral status register (PHS)
If a write operation is not performed in the correct sequence including access to the command register for the
protection-targeted internal registers, writing is not performed and a protection error is generated, setting the status
flag (PRERR) to 1. This flag is a cumulative flag. After checking the PRERR flag, it is cleared to 0 by an instruction.
This register can be read/written in 8-bit or 1-bit units.
7
6
PHS
0
0
Bit Position
Bit Name
0
PRERR
The operation conditions of the PRERR flag are as follows.
Set conditions:
<1> If the operation of the relevant store instruction for the on-chip peripheral I/O is not a write
<2> If the first store instruction operation after the write operation to the PHCMD register is for
Reset conditions: <1> If the PRERR flag of the PHS register is set to 0.
<2> If the system is reset
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CHAPTER 8 CLOCK GENERATION FUNCTION
5
4
3
0
0
0
Protection error
0: Protection error does not occur
1: Protection error occurs
operation for the PHCMD register, but the peripheral specific register is written to.
memory other than the specific registers and on-chip peripheral I/O.
User's Manual U14492EJ3V0UD
2
1
<0>
0
0
PRERR FFFFF802H
Function
Address
Initial value
00H
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