In-Service Priority Register (Ispr) - NEC V850E/IA1 mPD703116 User Manual

32-bit single-chip microcontrollers

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7.3.6 In-service priority register (ISPR)

This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request

is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and

remains set while the interrupt is serviced.

When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is

automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-maskable

interrupt servicing or exception processing.

This register is read-only in 8-bit or 1-bit units.

Caution In the interrupt enabled (EI) state, if an interrupt is acknowledged during the reading of the ISPR

acknowledgement.

acknowledgement, read it in the interrupt disabled (DI) state.

Bit Position

ISPR7 to ISPR0

Remark n = 0 to 7 (priority level)

CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION

To read the value of the ISPR register properly before interrupt

Indicates priority of interrupt currently acknowledged

0: Interrupt request with priority n not acknowledged

1: Interrupt request with priority n acknowledged

User's Manual U14492EJ3V0UD

Initial value