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7.3.8 Interrupt trigger mode selection
The valid edge of the INTPn, ADTRG0, ADTRG1, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11,
TCLR3, and TI3 pins can be selected by program. The edge that can be selected as the valid edge is one of the
following (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111).
• Rising edge
• Falling edge
• Both the rising and falling edges
When the INTPn, ADTRG0, ADTRG1, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11, TCLR3, and TI3
signals are edge-detected, they become an interrupt source or capture/trigger.
The valid edge is specified by external interrupt mode registers 1 and 2 (INTM1 and INTM2), signal edge selection
registers 10 and 11 (SESA10 and SESA11), the valid edge selection register (SESC), and TM2 input filter mode
registers 0 to 5 (FEM0 to FEM5).
(1) External interrupt mode registers 1, 2 (INTM1, INTM2)
These registers specify the valid edge for external interrupt requests (INTP0 to INTP6), input via external
pins. The correspondence between each register and the external interrupt requests that register controls is
shown below.
• INTM1: INTP0, INTP1, INTP2/ADTRG0, INTP3/ADTRG1
• INTM2: INTP4 to INTP6
INTP2 and INTP3 function alternately as ADTRG0 and ADTRG1 (A/D converter external trigger input).
Therefore, if the external trigger mode has been set by the TRG0 to TRG2 bits of A/D converter mode
register n0 (ADSCMn0), setting the ES20 and ES21, and ES30 and ES31 bits of INTM1 also specifies the
valid edge of the external trigger input (ADTRG0 and ADTRG1) (n = 0, 1).
The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and
falling edges).
These registers can be read/written in 8-bit or 1-bit units.
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User's Manual U14492EJ3V0UD
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