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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
9.2.5 Operation
(1) Basic operation
The following two operation modes can be selected for TM1n (n = 0, 1).
(a) General-purpose timer mode (CMD bit of TUMn register = 0)
In the general-purpose timer mode, the TM1n operates either as a 16-bit interval timer or as a PWM
output timer (count operation is up count only).
The base clock (f
the count clock is selected with the prescaler mode register (PRM1n).
(b) Up/down counter mode (UDC mode) (CMD bit of TUMn register = 1)
In the UDC mode, TM1n operates as a 16-bit up/down counter.
External clock input (TIUD1n, TCUD1n pins) by PRM1n register setting is used as the TM1n count clock.
The UDC mode is further divided into two modes according to the TM1n clear conditions.
• UDC mode A (TUMn register's CMD bit = 1, MSEL bit = 0)
The TM1n clear source can be selected as only external clear input (TCLR1n), a match signal
between the TM1n count value and the CM1n0 set value during up count operation, or logical sum
(OR) of the two signals, using bits CLR1 and CLR0 of the TMC1n register.
TM1n can reload the value of CM1n0 upon occurrence of TM1n underflow.
• UDC mode B (TUMn register's CMD bit = 1, MSEL bit = 1)
The status of TM1n after match of the TM1n count value and CM1n0 set value is as follows.
<1> In the case of up count operation, TM1n is cleared (0000H), and the INTCM1n0 interrupt is
generated.
<2> In the case of down count operation, the TM1n count value is decremented (−1).
The status of TM1n after match of the TM1n count value and CM1n1 set value is as follows.
<1> In the case of up count operation, the TM1n count value is incremented (+1).
<2> In the case of down count operation, TM1n is cleared (0000H), and the INTCM1n1 interrupt is
generated.
318
) to TM1n is selected with the timer 1/timer 2 clock selection register (PRM02), and
CLK
User's Manual U14492EJ3V0UD
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