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4.10 Boundary Operation Conditions
4.10.1 Program space
(1) Branching to the on-chip peripheral I/O area or successive fetches from the internal RAM area to the on-chip
peripheral I/O area are prohibited. If the above is performed (branching or successive fetch), a data to be
fetched is undefined and the operation is not guaranteed.
(2) If a branch instruction exists at the upper limit of the internal RAM area, a prefetch operation (invalid fetch)
that straddles over the on-chip peripheral I/O area does not occur.
(3) If a burst fetch is performed for contiguous memory blocks, it is terminated at the upper limit of a block, and
the start-up cycle is started at the lower limit of the next block.
(4) Burst fetch is valid only in the external memory area. In memory block 7, it is terminated when the internal
address count value has reached the upper limit of the external memory area.
4.10.2 Data space
The V850E/IA1 is provided with an address misalign function.
Through this function, regardless of the data format (word data or halfword data), data can be allocated to all
addresses. However, in the case of word data and halfword data, if the data is not subject to boundary alignment, the
bus cycle will be generated at least 2 times and bus efficiency will drop.
(1) In the case of halfword-length data access
When the address's LSB is 1, the byte-length bus cycle will be generated 2 times.
(2) In the case of word-length data access
(a) When the address's LSB is 1, bus cycles will be generated in the order of byte-length bus cycle,
halfword-length bus cycle, and byte-length bus cycle.
(b) When the address's lowest 2 bits are 10, the halfword-length bus cycle will be generated 2 times.
CHAPTER 4 BUS CONTROL FUNCTION
User's Manual U14492EJ3V0UD
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