Operation Modes - NEC V850E/IA1 mPD703116 User Manual

32-bit single-chip microcontrollers

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3.3 Operation Modes

Operation modes

The V850E/IA1 has the following operation modes. Mode specification is carried out by the MODE0 to MODE2

(1) Normal operation mode

(a) Single-chip modes 0, 1

Access to the internal ROM is enabled.

In single-chip mode 0, after the system reset is cleared, each pin related to the bus interface enters the

port mode, program execution branches to the reset entry address of the internal ROM, and instruction

processing starts. By setting the PMCDH, PMCDL, PMCCS, PMCCT, and PMCCM registers to control

mode by instruction, an external device can be connected to the external memory area.

In single-chip mode 1, after the system reset is cleared, each pin related to the bus interface enters the

control mode, program execution branches to the external device's (memory) reset entry address, and

instruction processing starts. The internal ROM area is mapped from address 100000H.

(b) ROMless modes 0, 1

After the system reset is cleared, each pin related to the bus interface enters the control mode, program

execution branches to the external device's (memory) reset entry address, and instruction processing

starts. Fetching of instructions and data access for internal ROM becomes impossible.

In ROMless mode 0, the data bus is a 16-bit data bus and in ROMless mode 1, the data bus is an 8-bit

(2) Flash memory programming mode ( µ µ µ µ PD70F3116 only)

If this mode is specified, it becomes possible for the flash programmer to run a program to the internal flash

The initial values of the registers differ depending on the mode.

Operation Mode

CHAPTER 3 CPU FUNCTION

ROMless mode 0

ROMless mode 1

Single-chip mode 0

Single-chip mode 1

User's Manual U14492EJ3V0UD

PMCCS PMCCT PMCCM