Control Register 3 (0X622); Irq Enable Register (0X623); Drive Links Low Register (0X624); Timers - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

56 SBC622 Hardware Reference Manual

3.2.16 Control Register 3 (0x622)

The SBC622 only implements bit 6 of this register.
This controls the LEDs.

Table 3-10 Control Register 3 (0x622)

Bits
D7
D6
D5
D4
D3 and D2
D1 and D0

3.2.17 IRQ Enable Register (0x623)

This register is not implemented on the SBC622.

3.2.18 Drive Links Low Register (0x624)

This register is not implemented on the SBC622.

3.2.19 Timers

The SBC622 provides two 32‐bit timers that are completely dedicated to user
applications and are not required for any standard system function. Each timer is
clocked by independent generators with selectable rates of 2 MHz, 1 MHz,
500 KHz and 250 KHz. Each timer may be independently enabled and each is
capable of generating a system interrupt on timeout.
Events can be timed by either polling the timers or enabling the interrupt
capability of the timer. A status register allows for application software to
determine which timer is the cause of any interrupt.
NOTE
Register definitions exist for four timers (two 16-bit and two 32-bit). The SBC622 only implements
the two 32-bit timers.
Meaning
BIT Pass (Green LED)
1 = LED lit
0 = LED off (default)
BIT Fail (Red LED)
1 = LED lit (default)
0 = LED off
BIT Status 1 (Yellow LED)
1 = LED lit
0 = LED off (default)
BIT Status 0 (Yellow LED)
1 = LED lit
0 = LED off (default)
RESERVED
RESERVED