Control Register 1 (0X620); Control Register 2 (0X621); Table 3-8 Control Register 1 (0X620); Table 3-9 Control Register 2 (0X621) - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

3.2.14 Control Register 1 (0x620)

The SBC622 only implements bit 0‐5, and bit 7 of this register.

Table 3-8 Control Register 1 (0x620)

Bit
D7
D6
D5
D4
D3
D2
D1
D0
NOTE
The WDT enable on the SBC622 is controlled by the Watchdog Timer CSR (location 0x60E).

3.2.15 Control Register 2 (0x621)

This controls the USB power and the COM ports. The SBC622 only implements
bits 1‐3 of this register. Note that on the SBC622, jumper E7 can override the
setting of these bits.

Table 3-9 Control Register 2 (0x621)

Bits
D7 USB Power enable 1 1 = Power on 0 = Power off (Default)
D6 USB Power enable 2 1 = Power on 0 = Power off (Default)
D5 and D4 COM mode, as follows:
D5
0
0
1
1
D3 COM2 RS422 select 1 = RS422 mode 0 = RS232 (default)
D2 COM1 RS422 select 1 = RS422 mode 0 = RS232 (default)
D1 COM buffer loopback 1 = Loopback enabled 0 = Loopback off (default)
D0 COM buffer enable 1 = COM buffer enabled 0 = COM buffer disabled (default)
Meaning
Sticky BIT (used by BIOS to know when board has been power cycled)
This bit is cleared to logic '0' by a power cycle
Watchdog WDT_TOUT Reset enable
1 = Enabled
0 = Disabled (default)
COM1/2 Buffer Enable
1 = Buffer Enabled (default)
0 = Buffer Disabled
ISP Data buffer enable
1 = Enabled
0 = Disabled (default)
BMM_PS0_ISP_VPP
Used to program the BMM, consult the factory for use
BMM_PS1_ISP_CLK
Used to program the BMM, consult the factory for use
BMM_PROGRAM_EN
Used to program the BMM, consult the factory for use
ISP Data out
Used to program the BMM, consult the factory for use
Meaning
D4 COM Mode
0 COM2
1 COM2 OFF
0 BMM
1 COM1
CPLD Control and Status Registers 55