Gpio Out Register (0X640); Gpio In Register (0X641); Table 3-15 Gpio Out Register (0X640); Table 3-16 Gpio In Register (0X641) - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

60 SBC622 Hardware Reference Manual
All GPIO inputs are double sampled at 33 MHz before being used by any internal
logic of the CPLD. For valid operation, input states must be valid for longer than
33 nS; pulses shorter than this may be missed due to the sampling of the inputs at
33 MHz. If rise and fall times of the GPIO are slow (>10 μS), then edge mode
should not be used as any noise on the edges can cause false triggering. On really
slow edges, software may need to filter the inputs.

3.2.31 GPIO Out Register (0x640)

This holds the GPIO out data.

Table 3-15 GPIO Out Register (0x640)

Bit GPIO Pin
D7 GPIO7
D6 GPIO6
D5 GPIO5
D4 GPIO4
D3 GPIO3
D2 GPIO2
D1 GPIO1
D0 GPIO0
NOTE
This register is only cleared on a power cycle.

3.2.32 GPIO In Register (0x641)

This reflects the current state of the GPIO pins regardless of whether they are
configured as inputs or outputs.

Table 3-16 GPIO In Register (0x641)

Bit GPIO Pin
D7 GPIO7
D6 GPIO6
D5 GPIO5
D4 GPIO4
D3 GPIO3
D2 GPIO2
D1 GPIO1
D0 GPIO0