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The Mobile Intel QM57 Express Chipset also includes a number of local processor
peripheral resources, including general purpose timers, an interrupt controller,
and Real‐Time Clock (RTC) circuit. See the Section Software Support on page 14.
2.1.3 Volatile Memory DDR3 Main Memory Array
The SBC622 provides volatile memory via the dual channel DDR3 memory
controller integrated into the Core i7 processor. The main memory array on
SBC622 is as follows:
• Two channels of DDR3‐1067 SDRAM components on a 72‐bit data bus with
ECC support (Total of 8 GBytes max).
• Bank 0 is a 4 GByte maximum array on Channel 0 with components soldered
to the main SBC622 PCB. Bank 1 is a 4 GByte maximum array on Channel 1
with components soldered to the main SBC622 PCB.
2.1.4 Non-Volatile Memories
NAND Flash
Up to 8 GByte of NAND flash is soldered to the board and presents itself to the
system as one or two SATA drives. The onboard flash drives may be disabled with
jumper E505.
2
I
C/SMBus
The SBC622 assembly includes EEPROM memory of at least 512 Kbit accessible
resources
via the SMBus of the PCH.
2.1.5 SPI Bus Resources
The SBC622 supports BIOS firmware code using the Mobile Intel QM57 Express
Chipset SPI bus channel. The BIOS firmware is contained in one 4 MByte size SPI
bus Flash part. The SPI flash parts can be in‐circuit programmed with updates
after initial programming of the SPI bus parts which occurs off of the unit.
2.1.6 LPC Bus Resources
The LPC bus on SBC622 supports the following resources:
• CPLD with two Standard UARTs that terminate at the front panel (COM1)
and rear access (COM2) for use with RS232/422 COM ports
2.1.7 Watchdog Timers
The SBC622 Watchdog Timer (WDT) is programmable from about 2 ms up to over
60 seconds. WDT disables after a reset; enable must be set for the WDT to operate.
2.1.8 Mezzanine
This product provides two sites supporting both PMC and XMC with appropriate
I/O located at Site 1 and Site 2. PMC Sites 1 and 2 are compliant with IEEE 1386.1‐
2001, "IEEE Standard Physical and Environmental Layers for PCI Mezzanine
Cards (PMC)".
• The PMC is 64‐bit, PCI‐X capable of up to 133 MHz operation
• The PMC site is capable of both 3.3 V and 5 V PCI signal levels
• The XMC site provides x4 PCIe capability, minimum x8 on Site 1
The PMC and XMC I/O is muxʹd (BIOS control) and routed to either P5/P6 (Site 1)
or P3/P4 (Site 2) per VITA 46.9.
Standard Features 41
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