Latency Timer (Lt7-Lt0) Bits 15-8; Chty/Clat Not Implemented Bits 31-24,7-0 - Motorola DSP56305 User Manual

6.6.10.2

Latency Timer (LT7-LT0) Bits 15-8

The read/write bits LT7-LT0 have two functions:
In the PCI mode (HM = $1): LT7-LT0 specify, in units of PCI bus clock cycles, the value
of the latency timer for this PCI bus master.
In the Universal Bus modes (HM = $2,$3) with HIRH cleared: LT7-LT0 specify, in units
of DSP56300 core clock cycles, the duration of the HIRQ pulse. The duration of the HIRQ
pulse is given by the following equation:
HIRQ_PULSE_WIDTH = (LT[7:0]_Value+ 1) • DSP56300_Core_clock_cycle
This bits can be written by the DSP56300 core in the Self Configuration mode (see
Section 6.7.2).
The personal hardware reset clears LT7-LT0.
6.6.10.3

CHTY/CLAT Not Implemented Bits 31-24,7-0

These not implemented bits are reserved for future expansion and should be written
with zeros for upward compatibility. They are read by the host processor as zeros.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
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