Introduction - Motorola DSP56305 User Manual

11.1

INTRODUCTION

The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high density circuit boards have led to
development of this proposed standard under the sponsorship of the Test Technology
Committee of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core
implementation supports circuit-board test strategies based on this standard.
The test logic includes a TAP that consists of five dedicated signal signals, a 16-state
controller, and three test data registers. A Boundary Scan Register (BSR) links all device
signal signals into a single shift register. The test logic, implemented with static logic
design, is independent of the device system logic. The DSP56300 core implementation
provides the following capabilities:
• Perform boundary scan operations to test circuit-board electrical continuity
(EXTEST).
• Bypass the DSP56300 core for a given circuit-board test by effectively reducing
the BSR to a single cell (BYPASS).
• Sample the DSP56300 core-based device system signals during operation and
transparently shift out the result in the BSR. Preload values to output signals prior
to invoking the EXTEST instruction (SAMPLE/PRELOAD).
• Disable the output drive to signals during circuit-board testing (HI-Z).
• Provide a means of accessing the On-Chip Emulation (OnCE) controller and
circuits to control a target system (ENABLE_ONCE).
• Provide a means of entering the Debug Mode of operation (DEBUG_REQUEST).
• Query identification information (manufacturer, part number and version) from a
DSP56300 core-based device (IDCODE).
• Force test data onto the outputs of a DSP56300 core-based device while replacing
its Boundary Scan Register in the serial data path with a single bit register
(CLAMP).
This section, which includes aspects of the JTAG implementation specific to the
DSP56300 core, is intended to be used with the supporting IEEE 1149.1 document. The
discussion includes those items required by the standard to be defined and, in certain
cases, provides additional information specific to the DSP56300 core implementation.
For internal details and applications of the standard, refer to the IEEE 1149.1 document.
Figure 11-1 shows a block diagram of the TAP port.
MOTOROLA DSP56305 User's Manual
JTAG Port
Introduction
11-3