Remaining Data Count (Rdc5-Rdc0) Bits 21-16; Dpsr Reserved Bits 23-22, 15-12 And 3; Host To Dsp Data Path - Motorola DSP56305 User Manual

6.5.6.13

Remaining Data Count (RDC5-RDC0) Bits 21-16

The read-only bits, RDC5-RDC0, indicate the PCI data phases remaining to complete a
PCI burst after the HI32 has completed a transaction as a PCI master. The RDC5-RDC0
bits are updated each time a transaction is terminated with the HI32 as a PCI master
(MARQ = 1).
If the transaction terminated normally, the value of RDC5-RDC0 will be $00 and TO = 0,
TRTY = 0, TDIS = 0, TAB = 0, MAB = 0.
If the master access counter was enabled and the burst was not completed for any reason
(typical examples being: the target initiated transaction termination or the HI32 was
required to generate a master initiated time-out transaction termination), the value of
RDC5-RDC0 will be the remaining number of data phases remaining to complete the
burst minus one (i.e. RDC = $2 signifies that there remain three more words to be
transferred to complete the burst). The length of the burst is limited by BL5-BL0 in the
DPMC.
6.5.6.14

DPSR Reserved Bits 23-22, 15-12 and 3

These bits are reserved for future expansion and are read as zeros.
6.5.7

Host To DSP Data Path

In PCI master data transfers (HM = $1) with FC≠$0, the host-to-DSP data path is a six
word deep, 24-bit wide FIFO. The host data is read into the host side of the FIFO (HTXR)
as 24-bit words, and the DSP56300 core reads 24-bit words from the DSP side (DRXR).
In PCI master data transfers (HM = $1) with FC = $0, and PCI target data transfers (HM
= $1) with HTF = $0, the host-to-DSP data path operates as a three word deep, 32-bit
wide FIFO. The host data is read into the HTXR as 32-bit words, and the DSP56300 core
reads from the DRXR 24-bit words. Each word read by the DSP56300 core contains
16-bits of data, right aligned and zero extended. The first word read by the DSP56300
core contains the two least significant bytes of the 32-bit word read into the HTXR. The
second word read by the DSP56300 core contains the two most significant bytes of the
32-bit word read into the HTXR.
In PCI target data transfers (HM = $1) with HTF≠$0 the host-to-DSP data path is a six
word deep, 24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the
DSP56300 core reads 24-bit words from the DRXR.
In Universal Bus mode data transfers, the host-to-DSP data path is a five word deep,
24-bit wide FIFO. The host writes 24-bit words to the HTXR, and the DSP56300 core
reads 24-bit words from the DRXR.
The DSP side of the host-to-DSP data FIFO is described below. For a detailed description
of the host side see Section 6.2.2.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
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