Table of Contents
Advertisement
7.5.3.5.4
Frame Sync Polarity
The FSP bit controls the polarity of the frame sync.
• When the FSP bit is cleared, the polarity of the frame sync is positive (i.e., the
frame sync signal is asserted high). The ESSI synchronizes on the leading edge of
the frame sync signal.
• When the FSP bit is set, the polarity of the frame sync is negative (i.e., the frame
sync is asserted low). The ESSI synchronizes on the trailing edge of the frame sync
signal.
The ESSI receiver looks for a receive frame sync edge (leading edge if FSP is cleared,
trailing edge if FSP is set) only when the previous frame is completed. If the frame sync
is asserted before the frame is completed (or before the last bit of the frame is received in
the case of a bit frame sync or a word length frame sync with FSR set), the current frame
sync is not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent, that is, a new frame sync does not have to follow
immediately the previous frame. Gaps of arbitrary periods can occur between frames.
All the enabled transmitters will be tri-stated during these gaps.
7.5.3.6
Selecting the Bit Shift Order for the Transmitter
Some devices, such as codecs, require a MSB-first data format. Other devices, such as
those that use the AES-EBU digital audio format, require the LSB first. To be compatible
with all formats, the shift registers in the ESSI are bidirectional. The MSB/LSB selection
is made by programming the SHFD bit in the CRB.
• If the SHFD bit is cleared, data is shifted into the Receive Shift Register MSB first
and shifted out of the Transmit Shift Register MSB first.
• If the SHFD bit is set, data is shifted into the Receive Shift Register LSB first and
shifted out of the Transmit Shift Register LSB first.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
DSP56305 User's Manual
Operating Modes
7-51
Advertisement
Chapters
Table of Contents
