Table 14-3 Ine[3:0], Oute[3:0] Bits And Their Respective Cfsrs; Output Enable Bits (Oute[3:0])—Csftb Bits 23–20; Ccop Control Status Register (Ccsr) - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
CCOP Programming Model

Table 14-3 INE[3:0], OUTE[3:0] Bits and their Respective CFSRs

When CCOP operates in the Parity Coding Mode Using One CFSR (OPM[1:0] = 10 in
CCSR), INE[3:1] are not applicable since only CFSRA is active (the remaining CFSRs are
disabled). INE0 is used to enable (INE0 = 1) or disable (INE0 = 0) data input to the
feedback path of the active CFSR. Data input to the feedforward path is always enabled
and is not affected by INEx bits.
When CCOP operates in the Parity Coding Mode Using Two Concatenated CFSRs
(OPM[1:0] = 11 in CCSR), INE[3:2] are not applicable since only CFSRA and CFSRB are
active while CFSRC and CFSRD are disabled. In this mode INE0 must be equal to INE1
for proper operation of the concatenated scheme. INE0 = INE1 = 1 enables the input data
bit to the feedback path of the concatenated CFSR. INE0 = INE1 = 0 disables the input
data bit to the feedback path of the concatenated CFSR. The input data to the
feedforward path is always enabled and not affected by INEx.
14.4.3.5 Output Enable bits (OUTE[3:0])—CSFTB Bits 23–20
The Output Enable bits (OUTE[3:0]) are used to enable output from CFSR[D:A]
respectively during the output phase. When OUTEx is cleared, the output bit from
CFSRz is gated, so it does not affect the final output data bit (generated by XORing all
enabled output bits from the CFSRs). When OUTEx bit is set, the output bit from CFSRz
is enabled, and it is XORed together with other CFSR enabled output bits to form the
output data bit that goes to the output buffer.
14.4.4

CCOP Control Status Register (CCSR)

The CCOP Control Status Register (CCSR) is a 24-bit read/write register used to control
and interrogate the operation of the CCOP. The CCSR bits are shown in Figure 14-8 and
are described in the following paragraphs. Control bits in the CCSR should not be
changed while the CCOP is operating, except for the interrupt enable bits, otherwise
improper operation may result. The control bits OPM[1:0] and LRC (which select the
CFSR configuration) should only be changed when CCOP is in the CCOP individual
14-14
Bit Number Register Letter
0
1
2
3
DSP56305 User's Manual
A
B
C
D
MOTOROLA