Table 9-2 Timer Control Bits - Motorola DSP56309 User Manual

Triple Timer Module
Triple Timer Module Programming Model
Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by
a hardware RESET signal or a software RESET instruction.
9.3.4.3 Timer Compare Interrupt Enable (TCIE) Bit 2
The TCIE bit is used to enable or disable the timer compare interrupts. Setting TCIE
enables the compare interrupts. In the timer, pulse width modulation (PWM), or
watchdog modes, a compare interrupt is generated after the counter value matches the
value of the TCPR. The counter starts counting up from the number loaded from the
TLR and if the TCPR value is N, an interrupt occurs after (N Ð M + 1) events, where M is
the value of TLR.
Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by a
hardware RESET signal or a software RESET instruction.
9.3.4.4 Timer Control (TC[3:0]) Bits 4-7
The four TC bits control the source of the timer clock, the behavior of the TIO signal, and
timer mode. Table 9-2 summarizes the TC bit functionality. There is a detailed
description of the timer operating modes in Section 9.4ÑTimer Operational Modes.
The TC bits are cleared by a hardware RESET signal or a software RESET instruction.
If the clock is external, the counter is incremented by the transitions on the
Note:
TIO signal. The external clock is internally synchronized to the internal clock,
and its frequency should be lower than the internal operating frequency
divided by 4 (CLK/4).
Note: To insure proper operation, the TC[3:0] bits should be changed only when the
timer is disabled (i.e., when the TE bit in the TCSR has been cleared).
Bit Settings
TC3 TC2 TC1
0 0 0
0 0 0
0 0 1
0 0 1
9-10

Table 9-2 Timer Control Bits

Mode
TC0
Number
0 0
1 1
0 2
1 3
DSP56309UM/D
Mode Characteristics
Mode Function
Timer and GPIO
Timer Pulse
Timer Toggle
Event Counter
TIO Clock
1 Internal
GPIO
Output Internal
Output Internal
Input External
MOTOROLA