Motorola DSP56305 User Manual page 580

24-bit digital signal processor
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Equates
;
Register Addresses Of DMA1
M_DSR1
EQU
$FFFFEB
M_DDR1
EQU
$FFFFEA
M_DCO1
EQU
$FFFFE9
M_DCR1
EQU
$FFFFE8
;
Register Addresses Of DMA2
M_DSR2
EQU
$FFFFE7
M_DDR2
EQU
$FFFFE6
M_DCO2
EQU
$FFFFE5
M_DCR2
EQU
$FFFFE4
;
Register Addresses Of DMA4
M_DSR3
EQU
$FFFFE3
M_DDR3
EQU
$FFFFE2
M_DCO3
EQU
$FFFFE1
M_DCR3
EQU
$FFFFE0
;
Register Addresses Of DMA4
M_DSR4
EQU
$FFFFDF
M_DDR4
EQU
$FFFFDE
M_DCO4
EQU
$FFFFDD
M_DCR4
EQU
$FFFFDC
;
Register Addresses Of DMA5
M_DSR5
EQU
$FFFFDB
M_DDR5
EQU
$FFFFDA
M_DCO5
EQU
$FFFFD9
M_DCR5
EQU
$FFFFD8
;
DMA Control Register
M_DSS
EQU
$3
M_DSS0
EQU
0
M_DSS1
EQU
1
M_DDS
EQU
$C
M_DDS0
EQU
2
M_DDS1
EQU
3
M_DAM
EQU
$3f0
M_DAM0
EQU
4
M_DAM1
EQU
5
M_DAM2
EQU
6
M_DAM3
EQU
7
M_DAM4
EQU
8
B-12
; DMA1 Source Address Register
; DMA1 Destination Address Register
; DMA1 Counter
; DMA1 Control Register
; DMA2 Source Address Register
; DMA2 Destination Address Register
; DMA2 Counter
; DMA2 Control Register
; DMA3 Source Address Register
; DMA3 Destination Address Register
; DMA3 Counter
; DMA3 Control Register
; DMA4 Source Address Register
; DMA4 Destination Address Register
; DMA4 Counter
; DMA4 Control Register
; DMA5 Source Address Register
; DMA5 Destination Address Register
; DMA5 Counter
; DMA5 Control Register
; DMA Source Space Mask (DSS0-Dss1)
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask (DDS-DDS1)
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
; DMA Address Mode Mask (DAM5-DAM0)
; DMA Address Mode 0
; DMA Address Mode 1
; DMA Address Mode 2
; DMA Address Mode 3
; DMA Address Mode 4
DSP56305 User's Manual
MOTOROLA

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