Motorola DSP56305 User Manual page 9

6.6.1.1 Transmit Request Enable (TREQ) Bit 1 . . . . . . . . . . . . . 6-55
6.6.1.2 Receive Request Enable (RREQ) Bit 2. . . . . . . . . . . . . . 6-56
6.6.1.3 Host Flags (HF2-HF0) Bits 5 and 3. . . . . . . . . . . . . . . . . 6-57
6.6.1.4 DMA Enable (DMAE) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . 6-57
6.6.1.5 Slave Fetch Type (SFT) Bit 7 . . . . . . . . . . . . . . . . . . . . . 6-58
6.6.1.6 Host Transmit Data Transfer Format (HTF1-HTF0)
Bits 9 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59
6.6.1.7 Host Receive Data Transfer Format (HRF1-HRF0)
Bits 11 and 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-63
6.6.1.8 Host Semaphores (HS2-HS0) Bits 16 and 14. . . . . . . . . 6-64
6.6.1.9 Target Wait State Disable (TWSD) Bit 19 . . . . . . . . . . . 6-64
6.6.1.10 HCTR Reserved Control
Bits 31-20, 18-17, 13, 10, and 0 . . . . . . . . . . . . . . . . . . . 6-67
6.6.2 HI32 Status Register (HSTR) . . . . . . . . . . . . . . . . . . . . . . . 6-68
6.6.2.1 Transmitter Ready (TRDY) Bit 0 . . . . . . . . . . . . . . . . . . . 6-69
6.6.2.2 Host Transmit Data Request (HTRQ) Bit 1 . . . . . . . . . . . 6-69
6.6.2.3 Host Receive Data Request (HRRQ) Bit 2 . . . . . . . . . . . 6-70
6.6.2.4 Host Flags (HF5-HF3) Bits 5, 4 and 3. . . . . . . . . . . . . . . 6-70
6.6.2.5 Host Interrupt A (HINT) Bit 6 . . . . . . . . . . . . . . . . . . . . . . 6-70
6.6.2.6 Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . . . . . . 6-71
6.6.2.7 HSTR Reserved Status Bits 31-8 . . . . . . . . . . . . . . . . . . 6-71
6.6.3 Host Command Vector Register (HCVR) . . . . . . . . . . . . . . 6-72
6.6.3.1 Host Command (HC) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . 6-73
6.6.3.2 Host Vector (HV6-HV0) Bits 7-1 . . . . . . . . . . . . . . . . . . . 6-74
6.6.3.3 Host Non-Maskable Interrupt (HNMI) Bit 15 . . . . . . . . . . 6-74
6.6.3.4 HCVR Reserved Bits 31-16, 14-8 . . . . . . . . . . . . . . . . . . 6-74
6.6.4 Host Slave Receive Data Register (HRXS) . . . . . . . . . . . . . 6-75
6.6.5 Host Master Receive Data Register (HRXM) . . . . . . . . . . . 6-76
6.6.6 Host Transmit Data Register (HTXR) . . . . . . . . . . . . . . . . . 6-76
6.6.7 Device/Vendor ID Configuration Register (CDID/CVID) . . . 6-78
6.6.8 Status/Command Configuration Register (CSTR/CCMR) . . 6-78
6.6.8.1 Memory Space Enable (MSE) Bit 1 . . . . . . . . . . . . . . . . 6-80
6.6.8.2 Bus Master Enable (BM) Bit 2. . . . . . . . . . . . . . . . . . . . . 6-80
6.6.8.3 Parity Error Response (PERR) Bit 6 . . . . . . . . . . . . . . . . 6-80
6.6.8.4 Wait Cycle Control (WCC) Bit 7 . . . . . . . . . . . . . . . . . . . 6-80
6.6.8.5 System Error Enable (SERE) Bit 8 . . . . . . . . . . . . . . . . . 6-81
MOTOROLA DSP56305 User's Manual vii