Viterbi Data Register/Fifo (Vdr); Viterbi Data Out Register (Vdor) - Motorola DSP56305 User Manual

13.5.1

Viterbi Data Register/FIFO (VDR)

The Viterbi Data Register/FIFO (VDR) holds the input data for the decoding, encoding,
and equalization operations. It is of variable depth according to rate and mode, with a
maximum depth of six locations, and is 16-bits wide. VDR can be accessed by the core
and DMA.
In decoding and equalization modes, "double-buffering" is implemented to obtain
maximum throughput.
In equalization the VDR (register) should be written with 16-bit word data obtained
from the Matched Filter (MF). In encoding, the VDR (register) holds a 1-bit hard-value
word ('0', '1' bit for encoding - $7FFF00, $800000 respectively). In both equalization and
encoding, one write access is required for every data request.
In decoding, the VDR (FIFO) should be written with 8-bit hard or soft data symbols, one
symbol-bit at a time; it should be written with a symbol for every data request. The write
of a symbol is composed of two, three, four, or six (depending on the code's rate - 1/2,
1/3, 1/4, 1/6 respectively) write accesses, each containing a soft symbol-bit occupying
the 8 most significant bits of the data word. The symbol-bit write order should match the
TAP polynomials (g(0), g(1), g(2),...etc.) starting with g(0).
13.5.2

Viterbi Data Out Register (VDOR)

The Viterbi Data Out Register (VDOR) is a 16-bit read-only register used for reading
data from the VCOP output buffer. The VDOR is used for encoding, decoding and
equalization. The VDOR can be accessed by the core and DMA.
In encoding, the VDOR holds (a hard-value of an encoded symbol-bit) or (the single bit
value of a decoded symbol). The value read is either $800000 for '1' or $7FFF00 for '0'.
The bits are read in ascending order; that is, the bit generated by Tap polynomial 0 is the
first one read.
In decoding, the VDOR holds the decoded bit in the same hard value format ($800000 for
'1' or $7FFF00 for '0') and should be written with 16-bit words of packed decoded bits.
In equalization, the VDOR holds a hard value.
Consecutive single cycle reads of VDOR are not allowed.
MOTOROLA DSP56305 User's Manual
VITERBI CO-PROCESSOR
Programming Model
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