Host Command Interrupt Enable (Hcie) Bit 0; Slave Transmit Interrupt Enable (Stie) Bit 1; Slave Receive Interrupt Enable (Srie) Bit 2; Host Flags (Hf[5:3]) Bits 5-3 - Motorola DSP56305 User Manual

6.5.1.1

Host Command Interrupt Enable (HCIE) Bit 0

Setting the HCIE bit enables a vectored DSP56300 core interrupt request if the host
command pending (HCP) status bit in the DSR is set. If HCIE is cleared, HCP interrupt
requests are disabled. The starting address of this interrupt is determined by the host
vector HV[6:0] in the host command vector register (HCVR).
If the host non-maskable interrupt (HNMI) bit is set in the host command vector register
(HCVR), HCIE is ignored, and an interrupt is generated if HCP is set regardless of HCIE.
Hardware and software resets clear HCIE.
6.5.1.2

Slave Transmit Interrupt Enable (STIE) Bit 1

The STIE bit, when set, enables an DSP56300 core interrupt request when the slave
transmit data request (STRQ) status bit in the DSR is set. If STIE is cleared, STRQ
interrupt requests are disabled.
Hardware and software resets clear STIE.
6.5.1.3

Slave Receive Interrupt Enable (SRIE) Bit 2

The SRIE bit, when set, enables a DSP56300 core interrupt request when the slave receive
data request (SRRQ) status bit in the DSR is set. If SRIE is cleared, SRRQ interrupt
requests are disabled.
Hardware and software resets clear SRIE.
6.5.1.4

Host Flags (HF[5:3]) Bits 5-3

The Host Flag (HF[5:3]) bits are used as general purpose flags for DSP-to-host
communication. HF[5:3] may be set or cleared by the DSP56300 core. HF[5:3] are visible
to the external host in the HSTR.
Hardware and software resets clear host flags.
There are six host flags: three used by the host to signal the DSP56300 core
Note:
(HF[2:0]) and three used by the DSP56300 core to signal the host processor
(HF[5:3]). These are general purpose flags. The host flags do not cause
interrupts; they must be polled to see if they have changed. These flags can be
used individually or as encoded triads.
6.5.1.5

Host Interrupt A (HINT) Bit 6

The HINT bit controls the HINTA signal. When HINT is set by the DSP56300 core, the
HINTA signal is driven low. When HINT is cleared by the DSP56300 core, the HINTA
signal is released.
Hardware and software resets clear HINT.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
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