Table 6-7 Dsp Pci Master Control Register (Dpmc); Dsp Pci Transaction Address (Ar31-Ar16) Bits 15-0 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.3 DSP PCI Master Control Register(DPMC)

Table 6-7 DSP PCI Master Control Register (DPMC)

11 10 9
AR27 AR26 AR25
23 22 21
FC1 FC0 BL5
Bit
15-0
21-16 BL[5:0]
23-22 FC[1:0]
The DPMC is a 24-bit read/write register used by the DSP56300 core to generate the two
most significant bytes of the 32-bit PCI transaction address, and to control the burst
length and the data transfer format. The DPMC cannot be accessed by the host
processor.
The DPMC may be written only if MARQ is set or in the Self Configuration mode. (See
Section 6.5).
The DPMC bits are described in the following paragraphs.
6.5.3.1

DSP PCI Transaction Address (AR31-AR16) Bits 15-0

The AR31-AR16 bits are the two most significant bytes of the 32-bit PCI transaction
address. The two least significant bytes of the PCI transaction address are located in the
DPAR register (see Section 6.5.4). When the DPAR is written by the DSP56300 core,
while in the PCI mode (HM = $1), the PCI ownership is requested and, when granted,
the HI32 will initiate a PCI transaction. The full 32-bit address (AR31-AR16 from the
DPMC and AR15-AR0 from the DPAR) is driven to the HAD31-HAD0 signals during
the PCI address phase.
Hardware and software resets clear AR31-AR16.
6-28
8 7 6
AR24 AR23 AR22
20 19 18
BL4 BL3 BL2
Name
AR[31:16] DSP PCI Transaction Address (High)
PCI Data Burst Length
Data Transfer Format Control
DSP56305 User's Manual
5 4 3
AR21 AR20 AR19
17 16 15
BL1 BL0 AR31
Function
2 1 0
AR18 AR17 AR16
14 13 12
AR30 AR29 AR28
MOTOROLA