Motorola DSP56305 User Manual page 251

Table 6-18 Host Port Signals - Detailed Description (Sheet 11 of 13)
HI32
Port
a
Pin
HCLK
Bus Clock
Input signal.
Provides timing for all transactions
on PCI. All other PCI signals are
sampled on the HCLK rising edge.
HP40-HP33 HAD31-HAD16
Address/Data Multiplexed Bus
Tri-state, bidirectional bus.
During the first clock of a transaction
HAD31-HAD0 contain the physical
byte address (32 bits). During
subsequent clock HAD31-HAD0
contain data.
PCI
UNUSED
Must be forced or pulled up to Vcc.
HD15-HD8
Data Bus
Tri-state, bidirectional bus.
Used to transfer data between the host processor and the
HI32.
This bus is released (disconnected) when the HI32 is not
selected by HA10-HA0. The HD15-HD0 signals are driven
by the HI32 during a read access, and are inputs to the
HI32 during a write access.
When operating with a host bus less than 16 bits wide, the
HD15-HD8 signals that are not used for transferring data
must be
operating with a 8-bit bus, HP40-HP33 must be
pulled up to Vcc or pulled down to GND.
NOTE: It is recommended to pull these unused data lines
to GND, as pulling these lines to Vcc will set the
corresponding bits in the HCTR, when the external host
writes to this register.
HI32 Mode
Enhanced Universal
pulled to Vc . For example: when
c or to GND
b
Universal
GPIO
Disconnected