Motorola DSP56305 User Manual page 75

Table 2-9 Interrupt and Mode Control (Continued)
Signal
Type
Name
MODB Input
IRQB Input
MODC Input
IRQC Input
MOTOROLA
State
During
Reset
Input Mode Select B—MODB selects the initial chip operating mode
during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input
IRQB during normal instruction processing. MODA, MODB,
MODC, and MODD select one of sixteen initial chip operating
modes, latched into the OMR when the RESET signal is
deasserted.
External Interrupt Request B—IRQB is an active-low
Schmitt-trigger input, internally synchronized to CLKOUT. If
IRQB is asserted synchronous to CLKOUT, multiple
processors can be re-synchronized using the WAIT instruction
and asserting IRQB to exit the Wait state. If the processor is in
the Stop standby state and IRQC is asserted, the processor will
exit the Stop state.
These inputs are 5 V tolerant.
Input Mode Select C—MODC selects the initial chip operating mode
during hardware reset and becomes a level-sensitive or
negative-edge-triggered, maskable interrupt request input
IRQC during normal instruction processing. MODA, MODB,
MODC, and MODD select one of sixteen initial chip operating
modes, latched into the OMR when the RESET signal is
deasserted.
External Interrupt Request C—IRQC is an active-low
Schmitt-trigger input, internally synchronized to CLKOUT. If
IRQC is asserted synchronous to CLKOUT, multiple
processors can be re-synchronized using the WAIT instruction
and asserting IRQC to exit the Wait state. If the processor is in
the Stop standby state and IRQC is asserted, the processor will
exit the Stop state.
These inputs are 5 V tolerant.
DSP56305 User's Manual
Signal/Connection Descriptions
Interrupt and Mode Control
Signal Description
2-17