D-Link DGE-560SX User Manual page 132

Register
A3 Interrupt
A4 Built-In
Self-Test
A5 PCI Cfg
Register
Group B: Memory Tests
B1 Scratch Pad
read-only bit and the read/write bits. The test writes 0s and 1s to
the test bits to ensure the read-only bits are not changed, and
that read/write bits are changed.
This test attempts to read the register configuration file
(Ctrlreg.txt) for the register definitions. If the file does not exist,
a default register offset and mask bits are used.
Offset Read-Only Mask
0x00000400 0x00000000
0x00000404 0x03800107
This test verifies the interrupt functionality. It enables an
interrupt and waits 500 ms for the interrupt to occur and reports
an error if it cannot generate the interrupt.
This is the hardware built-in self-test (BIST).
This test verifies the access integrity of the PCI configuration
registers.
This test tests the onboard scratchpad SRAM. The following tests
are performed:
Address Test. This test writes each address with a unique
increment of data and reads back data to ensure data is correct.
After filling the entire address with the unique data, the program
reads back the data again to ensure that the data is still correct.
Walking bit. For each address, data one is written and read back
for testing. Then it shifts the data left one bit, so the data
becomes two and repeats the same test. It repeats the test 32
times until the test bit is shifted out of the test address. The same
test is repeated for entire test range.
Pseudo-Random Data. A precalculated pseudo-random data
set is used to write unique data to each test RAM. After passing
the test, the program reads back the data one more time to
ensure that the data is still correct.
Data Read/Write Test: This test writes test data to the SRAM
and reads it back to ensure that the data is correct. The test data
used is 0x00000000, 0xFFFFFFFF, 0xAA55AA55, and
0x55AA55AA.
Alternate Data Pattern Test. This test writes test data into the
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D-Link DGE-560SX User Guide
Read/Write Mask
0x007FFF8C
0x00000000