Philips LPC213 Series User Manual page 88

Philips Semiconductors
Volume 1
Table 79:
Bit
0
1
2
7:3
9.3.6 UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read
Only)
The U0IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U0IIR access. If an interrupt occurs during
an U0IIR access, the interrupt is recorded for the next U0IIR access.
Table 80:
Bit
0
3:1
5:4
7:6
User manual
UART0 Interrupt Enable Register (U0IER - address 0xE000 C004, when DLAB = 0)
bit description
Symbol Value Description
RBR U0IER[0] enables the Receive Data Available interrupt
Interrupt for UART0. It also controls the Character Receive
Enable Time-out interrupt.
0 Disable the RDA interrupts.
1 Enable the RDA interrupts.
THRE U0IER[1] enables the THRE interrupt for UART0. The
Interrupt status of this can be read from U0LSR[5].
Enable
0 Disable the THRE interrupts.
1 Enable the THRE interrupts.
RX Line U0IER[2] enables the UART0 RX line status interrupts.
Status The status of this interrupt can be read from U0LSR[4:1].
Interrupt
Enable
0 Disable the RX line status interrupts.
1 Enable the RX line status interrupts.
- Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UART0 Interrupt Identification Register (UOIIR - address 0xE000 C008, read only)
bit description
Symbol Value Description
Interrupt Note that U0IIR[0] is active low. The pending interrupt can
Pending be determined by evaluating U0IIR[3:1].
0 At least one interrupt is pending.
1 No pending interrupts.
Interrupt U0IER[3:1] identifies an interrupt corresponding to the
Identification UART0 Rx FIFO. All other combinations of U0IER[3:1] not
listed above are reserved (000,100,101,111).
011 1 - Receive Line Status (RLS).
010 2a - Receive Data Available (RDA).
110 2b - Character Time-out Indicator (CTI).
001 3 - THRE Interrupt
- Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
FIFO Enable These bits are equivalent to U0FCR[0].
Rev. 01 — 24 June 2005
UM10120
Chapter 9: UART0
Reset
value
0
0
0
NA
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
1
0
NA
0
88