Philips LPC213 Series User Manual page 154

Philips Semiconductors
Volume 1
Table 129: SPI Status Register (S0SPSR - address 0xE002 0004) bit description
Bit
5
6
7
12.4.3 SPI Data Register (S0SPDR - 0xE002 0008)
This bi-directional data register provides the transmit and receive data for the SPI.
Transmit data is provided to the SPI by writing to this register. Data received by the SPI
can be read from this register. When a master, a write to this register will start a SPI data
transfer. Writes to this register will be blocked from when a data transfer starts to when the
SPIF status bit is set, and the status register has not been read.
Table 130: SPI Data Register (S0SPDR - address 0xE002 0008) bit description
Bit
7:0
15:8 DataHigh
12.4.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)
This register controls the frequency of a master's SCK. The register indicates the number
of PCLK cycles that make up an SPI clock. The value of this register must always be an
even number. As a result, bit 0 must always be 0. The value of the register must also
always be greater than or equal to 8. Violations of this can result in unpredictable
behavior.
Table 131: SPI Clock Counter Register (S0SPCCR - address 0xE002 000C) bit description
Bit
7:0
The SPI0 rate may be calculated as: PCLK / SPCCR0 value. The PCLK rate is
CCLK /VPB divider rate as determined by the VPBDIV register contents.
12.4.5 SPI Interrupt register (S0SPINT - 0xE002 001C)
This register contains the interrupt flag for the SPI0 interface.
User manual
Symbol Description
ROVR Read overrun. When 1, this bit indicates that a read overrun has
occurred. This bit is cleared by reading this register.
WCOL Write collision. When 1, this bit indicates that a write collision
has occurred. This bit is cleared by reading this register, then
accessing the SPI data register.
SPIF SPI transfer complete flag. When 1, this bit indicates when a SPI
data transfer is complete. When a master, this bit is set at the
end of the last cycle of the transfer. When a slave, this bit is set
on the last data sampling edge of the SCK. This bit is cleared by
first reading this register, then accessing the SPI data register.
Note: this is not the SPI interrupt flag. This flag is found in the
SPINT register.
Symbol Description
DataLow SPI Bi-directional data port.
If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some
or all of these bits contain the additional transmit and receive
bits. When less than 16 bits are selected, the more significant
among these bits read as zeroes.
Symbol Description
Counter SPI0 Clock counter setting.
Rev. 01 — 24 June 2005
UM10120
Chapter 12: SPI
Reset value
0
0
0
Reset value
0x00
0x00
Reset value
0x00
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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