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Philips Semiconductors
Volume 1
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that
can be found on official ARM website.
1.7 On-chip Flash memory system
The LPC2131/2/4/6/8 incorporates a 32, 64, 128, 256 and 512 kB Flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the Flash memory may be accomplished in several ways: over the serial builtin JTAG
interface, using In System Programming (ISP) and UART0, or by means of In Application
Programming (IAP) capabilities. The application program, using the IAP functions, may
also erase and/or program the Flash while the application is running, allowing a great
degree of flexibility for data storage field firmware upgrades, etc. When the
LPC2131/2/4/6/8 on-chip bootloader is used, 32/64/128/256/500 kB of Flash memory is
available for user code.
The LPC2131/2/4/6/8 Flash memory provides minimum of 10,000 erase/write cycles and
10 years of data-retention.
1.8 On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2131/2/4/6/8 provide
8/16/32 kB of static RAM respectively.
The LPC2131/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory.
Word and halfword accesses to the memory ignore the alignment of the address and
access the naturally-aligned value that is addressed (so a memory access ignores
address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).
Therefore valid reads and writes require data accessed as halfwords to originate from
addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in
hexadecimal nottaion) and data accessed as words to originate from adresses with
address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal
notation). This rule applies to both off and on-chip memory usage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during
back-to-back writes. The write-back buffer always holds the last data sent by software to
the SRAM. This data is only written to the SRAM when another write is requested by
software (the data is only written to the SRAM when software does another write). If a chip
reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after
a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that
checks SRAM contents after reset must take this into account. Two identical writes to a
location guarantee that the data will be present after a Reset. Alternatively, a dummy write
operation before entering idle or power-down mode will similarly guarantee that the last
data written will be present in SRAM after a subsequent Reset.
User manual
Rev. 01 — 24 June 2005
UM10120
Chapter 1: Introductory information
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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