Philips LPC213 Series User Manual page 159

Philips Semiconductors
Volume 1
The CPHA control bit selects the clock edge that captures data and allows it to change
state. It has the most impact on the first bit transmitted by either allowing or not allowing a
clock transition before the first data capture edge. When the CPHA phase control bit is
LOW, data is captured on the first clock edge transition. If the CPHA clock phase control
bit is HIGH, data is captured on the second clock edge transition.
13.3.4 SPI format with CPOL=0,CPHA=0
Single and continuous transmission signal sequences for SPI format with CPOL = 0,
CPHA = 0 are shown in
SCK
SSEL
MOSI MSB
MISO MSB
Fig 39. SPI frame format with CPOL=0 and CPHA=0 (a) single and b) continuous transfer)
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. This causes slave
data to be enabled onto the MISO input line of the master. Master's MOSI is enabled.
One half SCK period later, valid master data is transferred to the MOSI pin. Now that both
the master and slave data have been set, the SCK master clock pin goes HIGH after one
further half SCK period.
The data is now captured on the rising and propagated on the falling edges of the SCK
signal.
User manual
Figure
SCK
SSEL
MSB
MOSI
MSB
MISO
a) Motorola SPI frame format (single transfer) with CPOL=0 and CPHA=0
LSB
LSB
4 to 16 bits
b) Motorola SPI frame format (continuous transfer) with CPOL=0 and CPHA=0
•
The CLK signal is forced LOW
•
SSEL is forced HIGH
•
The transmit MOSI/MISO pad is in high impedance
Rev. 01 — 24 June 2005
39.
LSB
LSB Q
4 to 16 bits
MSB
Q MSB
UM10120
Chapter 13: SSP
LSB
LSB Q
4 to 16 bits
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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