Philips LPC213 Series User Manual page 203

Philips Semiconductors
Volume 1
Table 170: Interrupt Location Register (ILR - address 0xE002 4000) bit description
Bit
0
1
7:2
18.4.4 Clock Tick Counter Register (CTCR - 0xE002 4004)
The Clock Tick Counter is read only. It can be reset to zero through the Clock Control
Register (CCR). The CTC consists of the bits of the clock divider counter.
Table 171: Clock Tick Counter Register (CTCR - address 0xE002 4004) bit description
Bit
14:0
15
18.4.5 Clock Control Register (CCR - 0xE002 4008)
The clock register is a 5-bit register that controls the operation of the clock divide circuit.
Each bit of the clock register is described in
Table 172: Clock Control Register (CCR - address 0xE002 4008) bit description
Bit
0
1
3:2
4
7:5
18.4.6 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt
every time a counter is incremented. This interrupt remains valid until cleared by writing a
one to bit zero of the Interrupt Location Register (ILR[0]).
User manual
Symbol Description
RTCCIF When one, the Counter Increment Interrupt block generated an interrupt.
Writing a one to this bit location clears the counter increment interrupt.
RTCALF When one, the alarm registers generated an interrupt. Writing a one to
this bit location clears the alarm interrupt.
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Symbol Description
Clock Tick Prior to the Seconds counter, the CTC counts 32,768 clocks per
Counter second. Due to the RTC Prescaler, these 32,768 time increments may
not all be of the same duration. Refer to the
clock divider (prescaler)" on page 207
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Symbol Description
CLKEN Clock Enable. When this bit is a one the time counters are enabled.
When it is a zero, they are disabled so that they may be initialized.
CTCRST CTC Reset. When one, the elements in the Clock Tick Counter are
reset. The elements remain reset until CCR[1] is changed to zero.
CTTEST Test Enable. These bits should always be zero during normal
operation.
CLKSRC If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler,
as on earlier devices in the Philips Embedded ARM family. If this bit is
1, the CTC takes its clock from the 32 kHz oscillator that's connected to
the RTCX1 and RTCX2 pins (see
oscillator component selection"
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 01 — 24 June 2005
Section 18.6 "Reference
for details.
Table 172.
Section 18.7 "RTC external 32 kHz
for hardware details).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10120
Chapter 18: RTC
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