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Manuals and User Guides for Philips LPC2103. We have
1
Philips LPC2103 manual available for free PDF download: User Manual
Philips LPC2103 User Manual (279 pages)
Brand:
Philips
| Category:
Microcontrollers
| Size: 5.3 MB
Table of Contents
: Pin Configuration
60
Chapter 1: General Information
3
Introduction
3
Features
3
Applications
4
Device Information
4
Architectural Overview
4
Chapter 22 : Supplementary Information
5
ARM7TDMI-S Processor
5
On-Chip Flash Memory System
5
On-Chip Static RAM (SRAM)
6
Block Diagram
7
Block
8
Chapter 2: LPC2101/02/03 Memory Addressing
8
Memory Maps
8
Memory Map Concepts and Operating Modes 11 Memory Re-Mapping
12
Prefetch Abort and Data Abort Exceptions
13
Chapter 3: System Control Block
15
Pin Description
15
Summary of System Control Block Functions
15
Crystal Oscillator
16
Register Description
16
External Interrupt Inputs
18
External Interrupt Flag Register (EXTINT - 0Xe01F C140)
19
Register Description
19
Interrupt Wake-Up Register (INTWAKE - 0Xe01F C144)
20
External Interrupt Mode Register (EXTMODE - 0Xe01F C148)
21
External Interrupt Polarity Register (EXTPOLAR - 0Xe01F C14C)
21
Other System Controls
22
Memory Mapping Control
23
Memory Mapping Control Register (MEMMAP - 0Xe01F C040)
23
Memory Mapping Control Usage Notes
23
System Control and Status Flags Register (SCS - 0Xe01F C1A0)
23
Phase Locked Loop (PLL)
24
Register Description
24
PLL Control Register (PLLCON - 0Xe01F C080)
26
PLL Configuration Register (PLLCFG - 0Xe01F C084)
27
PLL Status Register (PLLSTAT - 0Xe01F C088)
27
PLL Interrupt
28
PLL Modes
28
PLL and Power-Down Mode
29
PLL Feed Register (PLLFEED - 0Xe01F C08C)
29
PLL Frequency Calculation
29
PLL Configuring Examples
30
Procedure for Determining PLL Settings
30
Power Control
31
Register Description
31
Power Control for Peripherals Register (PCONP - 0Xe01F COC4)
32
Power Control Register (PCON - 0Xe01F COCO)
32
Power Control Usage Notes
33
Reset
33
Reset Source Identification Register (RSIR - 0Xe01F C180)
35
APB Divider
36
APBDIV Register (APBDIV - 0Xe01F C100)
36
Register Description
36
Wake-Up Timer
37
Code Security Vs. Debugging
38
Chapter 4 : Memory Acceleration Module (MAM)
39
Introduction
39
Operation
39
Flash Memory Bank
40
Instruction Latches and Data Latches
40
MAM Blocks
40
Flash Programming Issues
41
MAM Operating Modes
41
MAM Configuration
42
MAM Control Register (MAMCR - 0Xe01F C000)
42
Register Description
42
MAM Timing Register (MAMTIM - 0Xe01F C004)
43
MAM Usage Notes
43
Chapter 5: Vectored Interrupt Controller (VIC)
44
Description
44
Features
44
Register Description
44
Software Interrupt Register (Vicsoftint - 0Xffff F018)
46
VIC Registers
46
Software Interrupt Clear Register (Vicsoftintclear - 0Xffff F01C)
47
0Xffff F008)
48
0Xffff F010)
48
Raw Interrupt Status Register
48
Interrupt Enable Clear Register (Vicintenclear - 0Xffff F014)
49
Interrupt Enable Register
49
Interrupt Select Register (Vicintselect - 0Xffff F00C)
49
IRQ Status Register (Vicirqstatus -
50
FIQ Status Register (Vicfiqstatus - 0Xffff F004)
51
Vector Control Registers 0-15 (Vicvectcntl0-15 - 0Xffff F200-23C)
51
Default Vector Address Register (Vicdefvectaddr - 0Xffff F034)
52
Protection Enable Register (Vicprotection - 0Xffff F020)
52
Vector Address Register (Vicvectaddr - 0Xffff F030)
52
Vector Address Registers 0-15 (Vicvectaddr0-15 - 0Xffff F100-13C)
52
Interrupt Sources
53
Details and Case Studies on Spurious Interrupts
55
Spurious Interrupts
55
Solution 1: Test for an IRQ Received During a Write to Disable Irqs
56
Workaround
56
Solution 2: Disable Irqs and Fiqs Using Separate Writes to the CPSR
57
Solution 3: Re-Enable Fiqs at the Beginning of the IRQ Handler
57
VIC Usage Notes
57
Table of Contents
60
LPC2101/2102/2103 Pinout
60
P0.21/Ssel1/Mat3.0
61
Pin Description for LPC2101/02/03
61
Chapter 6 : Pin Configuration
61
Vbat
64
Chapter 7 : Pin Connect Block
66
Applications
66
Description
66
Features
66
Register Description
66
Pin Function Select Register 0 (PINSEL0 - 0Xe002 C000)
67
Pin Function Select Register 1 (PINSEL1 - 0Xe002 C004)
68
Reserved
68
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
70
Pin Function Select Register Values
70
Applications
71
Chapter 8 : General Purpose Input/Output Ports (GPIO)
71
Features
71
Pin Description
71
Register Description
71
Rev. 01 — 12 January
71
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
72
GPIO Port 0 Direction Register (IODIR, Port 0: IO0DIR - 0Xe002 8008; FIODIR, Port 0: FIO0DIR - 0X3Fff C000)
73
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
73
Fast GPIO Port 0 Mask Register (FIOMASK, Port 0: FIO0MASK - 0X3Fff C010)
74
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
74
GPIO Port 0 Pin Value Register (IOPIN, Port 0: IO0PIN - 0Xe002 8000; FIOPIN, Port 0: FIO0PIN - 0X3Fff C014)
75
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
75
GPIO Port 0 Output Set Register (IOSET, Port 0: IO0SET - 0Xe002 8004; FIOSET, Port 0: FIO0SET - 0X3Fff C018)
76
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
76
GPIO Port 0 Output Clear Register (IOCLR, Port 0: IO0CLR - 0Xe002 800C; FIOCLR, Port 0: FIO0CLR - 0X3Fff C01C)
77
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
77
Example 1: Sequential Accesses to IOSET and IOCLR Affecting the same GPIO Pin/Bit
78
GPIO Usage Notes
78
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
78
Example 2: an Immediate Output of 0S and 1S on a GPIO Port
79
Koninklijke Philips Electronics N.V. 2006. All Rights Reserved
79
Output Signal Frequency Considerations When Using the Legacy and Enhanced GPIO Registers
79
Writing to IOSET/IOCLR Vs. IOPIN
79
Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)
82
Features
82
Pin Description
82
Register Description
82
UART0 Divisor Latch Registers (U0DLL - 0Xe000 C000 and U0DLM - 0Xe000 C004, When DLAB = 1)
84
UART0 Receiver Buffer Register (U0RBR - 0Xe000 C000, When DLAB = 0, Read Only)
84
UART0 Transmit Holding Register (U0THR - 0Xe000 C000, When DLAB = 0, Write Only)
84
UART0 Fractional Divider Register (U0FDR - 0Xe000 C028)
85
UART0 Baudrate Calculation
86
UART0 Interrupt Enable Register (U0IER - 0Xe000 C004, When DLAB = 0)
87
UART0 Interrupt Identification Register (U0IIR - 0Xe000 C008, Read Only)
88
UART0 FIFO Control Register
90
0Xe000 C008)
90
UART0 Line Control Register
90
0Xe000 C00C)
90
UART0 Line Status Register
91
0Xe000 C014, Read Only)
91
UART0 Scratch Pad Register
92
0Xe000 C01C)
92
Auto-Baud
93
UART0 Auto-Baud Control Register
93
0Xe000 C020)
93
UART0 Transmit Enable Register
94
0Xe000 C030)
94
Auto-Baud Modes
95
Architecture
96
Chapter 10 : Universal Asynchronous Receiver/Transmitter 1 (UART1)
99
Features
99
Pin Description
99
Register Description
99
UART1 Divisor Latch Registers 0 and 1 (U1DLL - 0Xe001 0000 and U1DLM - 0Xe001 0004, When
101
UART1 Fractional Divider Register (U1FDR - 0Xe001 0028)
102
UART1 Baudrate Calculation
103
UART1 Interrupt Enable Register (U1IER - 0Xe001 0004, When DLAB = 0)
104
UART1 Interrupt Identification Register (U1IIR - 0Xe001 0008, Read Only)
105
UART1 FIFO Control Register (U1FCR - 0Xe001 0008)
107
UART1 Line Control Register (U1LCR - 0Xe001 000C)
108
UART1 Modem Control Register (U1MCR - 0Xe001 0010)
109
UART1 Line Status Register (U1LSR - 0Xe001 0014, Read Only)
111
UART1 Modem Status Register (U1MSR - 0Xe001 0018)
112
UART1 Auto-Baud Control Register (U1ACR - 0Xe001 0020)
113
UART1 Scratch Pad Register (U1SCR - 0Xe001 001C)
113
Auto-Baud
114
Auto-Baud Modes
115
UART1 Transmit Enable Register (U1TER - 0Xe001 0030)
116
Architecture
117
Applications
119
Chapter 11: I 2 C Interfaces I 2 C0 and I 2 C1
119
Description
119
Features
119
I 2 C Operating Modes
120
Master Transmitter Mode
120
Pin Description
120
Master Receiver Mode
121
Slave Receiver Mode
122
I 2 C Implementation and Operation
123
Input Filters and Output Stages
123
Slave Transmitter Mode
123
Address Register, I2ADDR
125
Arbitration and Synchronization Logic
125
Comparator
125
Shift Register, I2DAT
125
Serial Clock Generator
126
Timing and Control
126
Control Register, I2CONSET and I2CONCLR
127
Register Description
127
Status Decoder and Status Register
127
C Control Set Register (I2CONSET: I2C0, I2C0CONSET - 0Xe001 C000 and I2C1, I2C1CONSET - 0Xe005 C000)
128
(I2STAT: 2 C Status Register
130
I 2 C Control Clear Register
130
I 2 C Data Register
131
I 2 C SCL HIGH Duty Cycle Register
131
I 2 C SCL Low Duty Cycle Register
131
I 2 C Slave Address Register
131
Selecting the Appropriate I C Data Rate and Duty Cycle
131
Details of I C Operating Modes
132
Master Transmitter Mode
133
Master Receiver Mode
134
Slave Receiver Mode
134
Slave Transmitter Mode
139
I2STAT = 0X00
145
I2STAT = 0Xf8
145
Miscellaneous States
145
Data Transfer after Loss of Arbitration
146
Forced Access to the I C-Bus
146
Simultaneous Repeated START Conditions from Two Masters
146
Some Special Cases
146
Bus Error
147
C-Bus Obstructed by a LOW Level on SCL or SDA
147
C State Service Routines
148
Initialization
148
Adapting State Services to an Application
149
C Interrupt Service
149
Initialization Routine
149
Software Example
149
Start Master Transmit Function
149
Start Master Receive Function
149
The State Service Routines
149
I 2 C Interrupt Routine
150
Master States
150
Non Mode Specific States
150
State: 0X00
150
State: 0X08
150
State: 0X10
150
Master Transmitter States
151
State: 0X18
151
State: 0X20
151
State: 0X28
151
State: 0X30
151
State: 0X38
152
Master Receive States
152
State: 0X40
152
State: 0X48
152
State: 0X50
152
State: 0X58
152
Slave Receiver States
153
State: 0X60
153
State: 0X68
153
State: 0X70
153
State: 0X78
153
State: 0X80
154
State: 0X88
154
State: 0X90
154
State: 0X98
154
State: 0Xa0
154
Slave Transmitter States
155
State: 0Xa8
155
State: 0Xb0
155
State: 0Xb8
155
State: 0Xc0
155
State: 0Xc8
155
Chapter 12: SPI Interface (SPI0)
157
Description
157
Features
157
SPI Data Transfers
157
SPI Overview
157
General Information
159
Master Operation
159
Exception Conditions
160
Read Overrun
160
Slave Operation
160
Write Collision
160
Mode Fault
161
Pin Description
161
Register Description
161
Slave Abort
161
SPI Control Register (S0SPCR - 0Xe002 0000)
162
SPI Status Register (S0SPSR - 0Xe002 0004)
163
Architecture
164
SPI Data Register (S0SPDR - 0Xe002 0008) 164 SPI Clock Counter Register (S0SPCCR - 0Xe002 000C)
164
SPI Interrupt Register (S0SPINT - 0Xe002 001C)
164
Chapter 13: SSP Controller (SPI1)
166
Description
166
Features
166
Bus Description
167
Texas Instruments Synchronous Serial (SSI) Frame Format
167
Clock Polarity (CPOL) and Clock Phase (CPHA) Control
168
SPI Frame Format
168
SPI Format with CPOL=0,CPHA=0
169
SPI Format with CPOL=0,CPHA=1
170
SPI Format with CPOL = 1,CPHA = 0
171
Semiconductor Microwire Frame Format
172
SPI Format with CPOL = 1,CPHA = 1
172
Register Description
174
Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
174
SSP Control Register 0 (SSPCR0 - 0Xe006 8000)
175
SSP Control Register 1 (SSPCR1 - 0Xe006 8004)
176
SSP Clock Prescale Register
177
0Xe006 8010)
177
SSP Data Register
177
0Xe006 8008)
177
SSP Status Register
177
0Xe006 800C)
177
SSP Interrupt Mask Set/Clear Register
178
0Xe006 8014)
178
SSP Raw Interrupt Status Register
178
0Xe006 8018)
178
SSP Interrupt Clear Register (SSPICR - 0Xe006 8020)
179
SSP Masked Interrupt Register (SSPMIS - 0Xe006 801C)
179
Chapter 14 : Analog-To-Digital Converter (ADC)
180
Description
180
Features
180
Pin Description
180
Register Description
181
A/D Control Register (AD0CR - 0Xe003 4000)
182
A/D Global Data Register (AD0GDR - 0Xe003 4004)
183
A/D Interrupt Enable Register (ADINTEN, ADC0: AD0INTEN - 0Xe003 400C)
184
A/D Status Register (ADSTAT, ADC0: AD0CR - 0Xe003 4004)
184
A/D Data Registers (ADDR0 to ADDR7, ADC0: AD0DR0 to AD0DR7 - 0Xe003 4010 to 0Xe003 402C)
185
Accuracy Vs. Digital Receiver
186
Hardware-Triggered Conversion
186
Interrupts
186
Operation
186
Applications
187
Chapter 15: Timer/Counter Timer0 and Timer1
187
Description
187
Features
187
Pin Description
188
Register Description
188
Interrupt Register (IR, TIMER0: T0IR - 0Xe000 4000 and TIMER1: T1IR - 0Xe000 8000)
190
Timer Control Register (TCR, TIMER0: T0TCR - 0Xe000 4004 and TIMER1: T1TCR - 0Xe000 8004)
190
Count Control Register (CTCR, TIMER0: T0CTCR - 0Xe000 4070 and TIMER1: T1TCR - 0Xe000 8070)
191
Count Control Register
192
Match Registers (MR0 - MR3)
192
Prescale Counter Register (PC, TIMER0: T0PC - 0Xe000 4010 and TIMER1: T1PC - 0Xe000 8010)
192
Prescale Register (PR, TIMER0: T0PR - 0Xe000 400C and TIMER1: T1PR - 0Xe000 800C)
192
Timer Counter (TC, TIMER0: T0TC - 0Xe000 4008 and TIMER1: T1TC - 0Xe000 8008)
192
Match Control Register (MCR, TIMER0: T0MCR - 0Xe000 4014 and TIMER1: T1MCR - 0Xe000 8014)
193
Capture Control Register (CCR, TIMER0: T0CCR - 0Xe000 4028 and TIMER1: T1CCR - 0Xe000 8028)
194
Capture Registers (CR0 - CR3)
194
External Match Register (EMR, TIMER0: T0EMR - 0Xe000 403C; and TIMER1: T1EMR - 0Xe000 803C)
195
PWM Control Register (PWMCON, TIMER0: PWM0CON - 0Xe000 4074 and TIMER1: PWM1CON - 0Xe000 8074)
196
Example Timer Operation
197
Rules for Single Edge Controlled PWM Ouputs
197
Architecture
198
Applications
200
Chapter 16 : Timer/Counter Timer2 and Timer3
200
Description
200
Features
200
P0.9 0
201
Pin Description
201
Register Description
201
Interrupt Register (IR TIMER2: T2IR -
203
Timer Control Register (TCR, TIMER2: T2TCR - 0Xe007 0004 and TIMER3: T3TCR - 0Xe007 4004)
203
Match Registers (MR0 - MR3)
205
Prescale Counter Register (PC, TIMER2: T2PC - 0Xe007 0010 and TIMER3: T3PC - 0Xe007 4010)
205
Prescale Register (PR, TIMER2: T2PR - 0Xe007 000C and TIMER3: T3PR - 0Xe007 400C)
205
Timer Counter (TC, TIMER2: T2TC - 0Xe007 0008 and TIMER3: T3TC - 0Xe007 4008)
205
Match Control Register (MCR, TIMER2: T2MCR - 0Xe007 0014 and TIMER3: T3MCR - 0Xe007 4014)
206
Capture Control Register (CCR, TIMER2: T2CCR - 0Xe007 0028 and TIMER3: T3CCR - 0Xe007 4028)
207
Capture Registers (CR0 - CR3)
207
External Match Register (EMR, TIMER2: T2EMR - 0Xe007 003C; and TIMER3: T3EMR - 0Xe007 403C)
208
Ouputs
209
PWM Control Register (PWMCON, TIMER0: PWM0CON - 0Xe007 0074 and TIMER1: PWM1CON - 0Xe007 4074)
209
Example Timer Operation
210
Architecture
211
Architecture
213
Chapter 17: Real Time Clock
213
Description
213
Features
213
Register Description
214
Interrupt Location Register (ILR - 0Xe002 4000)
215
Miscellaneous Register Group
215
RTC Interrupts
215
Clock Control Register (CCR - 0Xe002 4008)
216
Clock Tick Counter Register (CTC - 0Xe002 4004)
216
Counter Increment Interrupt Register (CIIR - 0Xe002 400C)
216
Alarm Mask Register (AMR - 0Xe002 4010)
217
Consolidated Time Register 0 (CTIME0 - 0Xe002 4014)
217
Consolidated Time Registers
217
Consolidated Time Register 1 (CTIME1 - 0Xe002 4018)
218
Consolidated Time Register 2 (CTIME2 - 0Xe002 401C)
218
Time Counter Group
218
Alarm Register Group
219
Leap Year Calculation
219
Reference Clock Divider (Prescaler)
220
RTC Usage Notes
220
Example of Prescaler Usage
221
Prescaler Fraction Register (PREFRAC - 0Xe002 4084)
221
Prescaler Integer Register (PREINT - 0Xe002 4080)
221
Prescaler Operation
222
RTC External 32 Khz Oscillator Component Selection
223
Applications
225
Chapter 18: Watchdog Timer (WDT)
225
Description
225
Features
225
Register Description
226
Watchdog Mode Register (WDMOD - 0Xe000 0000)
226
Block Diagram
227
Watchdog Feed Register (WDFEED - 0Xe000 0008)
227
Watchdog Timer Constant Register (WDTC - 0Xe000 0004)
227
Watchdog Timer Value Register (WDTV - 0Xe000 000C)
227
Applications
229
Chapter 19: Flash Memory System and Programming
229
Description
229
Features
229
Flash Boot Loader
229
Memory Map after any Reset
229
Criterion for Valid User Code
230
Communication Protocol
231
ISP Command Format
231
ISP Data Format
231
ISP Flow Control
231
ISP Response Format
231
Interrupts During IAP
232
Interrupts During ISP
232
ISP Command Abort
232
RAM Used by IAP Command Handler
232
RAM Used by ISP Command Handler
232
RAM Used by Realmonitor
232
Boot Process Flowchart
233
Sector Numbers
233
Flash Content Protection Mechanism
234
Code Read Protection (CRP)
235
ISP Commands
235
Set Baud Rate <Baud Rate> <Stop Bit
236
Unlock <Unlock Code
236
Echo <Setting
237
Read Memory <Address> <No. of Bytes
237
Write to RAM <Start Address> <Number of Bytes
237
Prepare Sector(S) for Write Operation <Start Sector Number> <End Sector Number
238
Copy RAM to Flash <Flash Address> <RAM Address> <No of Bytes
239
Go <Address> <Mode
239
Blank Check Sector(S) <Sector Number> <End Sector Number
240
Erase Sector(S) <Start Sector Number> <End Sector Number
240
Read Part Identification Number
240
Compare <Address1> <Address2> <No of Bytes
241
ISP Return Codes
241
Read Boot Code Version Number
241
19.9 Iap Commands
242
IAP Commands
242
Prepare Sector(S) for Write Operation
244
Copy RAM to Flash
245
Count_Error
245
Blank Check Sector(S)
246
Erase Sector(S)
246
Read Part Identification Number
246
Sector_Not_Blank
246
Addr_Error
247
Addr_Not_Mapped
247
Compare <Address1> <Address2> <No of Bytes
247
Compare_Error
247
Read Boot Code Version Number
247
Reinvoke ISP
247
IAP Status Codes
248
JTAG Flash Programming Interface
248
Chapter 20: Embeddedice Logic
249
Applications
249
Description
249
Features
249
Pin Description
250
Reset State of Multiplexed Pins
250
Block Diagram
251
Register Description
251
DEBUG Mode
252
Enable Debug Mode
252
JTAG Pin Selection
253
Applications
254
Chapter 21: Realmonitor
254
Description
254
Features
254
Realmonitor Components
255
Rmhost
255
Rmtarget
255
How Realmonitor Works
256
Adding Stacks
257
How to Enable Realmonitor
257
IRQ Mode
257
SVC Mode
257
Undef Mode
257
Data Abort Mode
258
FIQ Mode
258
Handling Exceptions
258
Prefetch Abort Mode
258
Realmonitor Exception Handling
258
User/System Mode
258
Code Example
259
Rmtarget Initialization
259
Realmonitor Build Options
262
Fig 14. LQFP48 Pin Configuration
270
User Manual
272
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