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Philips Semiconductors
Volume 1
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
CPHA = 0
Cycle # CPHA = 0
MOSI (CPHA = 0)
MISO (CPHA = 0)
CPHA = 1
Cycle # CPHA = 1
MOSI (CPHA = 1)
MISO (CPHA = 1)
Fig 36. SPI data transfer format (CPHA = 0 and CPHA = 1)
The data and clock phase relationships are summarized in
summarizes the following for each setting of CPOL and CPHA.
Table 125: SPI data to clock phase relationship
CPOL and CPHA settings
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
The definition of when an 8 bit transfer starts and stops is dependent on whether a device
is a master or a slave, and the setting of the CPHA variable.
When a device is a master, the start of a transfer is indicated by the master having a byte
of data that is ready to be transmitted. At this point, the master can activate the clock, and
begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
User manual
1
2
3
BIT 1
BIT 2
BIT 3
BIT 1
BIT 2
BIT 3
1
2
BIT 1
BIT 2
BIT 1
BIT 2
•
When the first data bit is driven
•
When all other data bits are driven
•
When data is sampled
Firsta data driven
Prior to first SCK rising edge
First SCK rising edge
Prior to first SCK falling edge SCK rising edge
First SCK falling edge
Rev. 01 — 24 June 2005
4
5
6
BIT 4
BIT 5
BIT 6
BIT 4
BIT 5
BIT 6
3
4
5
BIT 3
BIT 4
BIT 5
BIT 6
BIT 3
BIT 4
BIT 5
BIT 6
Other data driven
SCK falling edge
SCK rising edge
SCK falling edge
UM10120
Chapter 12: SPI
7
8
BIT 7
BIT 8
BIT 7
BIT 8
6
7
8
BIT 7
BIT 8
BIT 7
BIT 8
Table
125. This table
Data sampled
SCK rising edge
SCK falling edge
SCK falling edge
SCK rising edge
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
148
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