Philips LPC213 Series User Manual page 187

Philips Semiconductors
Volume 1
Table 155: Pulse Width Modulator (PWM) register map
Name Description
PWMMR6 PWM Match Register 6. PWMMR6 can be enabled through PWMMCR to
reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate
an interrupt when it matches the PWMTC. In addition, a match between
PWMMR6 and the PWMTC clears PWM6 in either single-edge mode or
double-edge mode.
PWMPCR PWM Control Register. Enables PWM outputs and selects PWM channel
types as either single edge or double edge controlled.
PWMLER PWM Latch Enable Register. Enables use of new PWM match values.
[1]
15.4.1 PWM Interrupt Register (PWMIR - 0xE001 4000)
The PWM Interrupt Register consists of eleven bits
interrupts and four reserved for the future use. If an interrupt is generated then the
corresponding bit in the PWMIR will be high. Otherwise, the bit will be low. Writing a logic
one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect.
Table 156: PWM Interrupt Register (PWMIR - address 0xE001 4000) bit description
Bit Symbol
0 PWMMR0 Interrupt
1 PWMMR1 Interrupt
2 PWMMR2 Interrupt
3 PWMMR3 Interrupt
7:4 -
8 PWMMR4 Interrupt
9 PWMMR5 Interrupt
10 PWMMR6 Interrupt
15:11 -
15.4.2 PWM Timer Control Register (PWMTCR - 0xE001 4004)
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM
Timer Counter. The function of each of the bits is shown in
User manual
Reset value relects the data stored in used bits only. It does not include reserved bits content.
Description
Interrupt flag for PWM match channel 0.
Interrupt flag for PWM match channel 1.
Interrupt flag for PWM match channel 2.
Interrupt flag for PWM match channel 3.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Interrupt flag for PWM match channel 4.
Interrupt flag for PWM match channel 5.
Interrupt flag for PWM match channel 6.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 01 — 24 June 2005
UM10120
Chapter 15: PWM
Access Reset Address
[1]
value
R/W 0 0xE001 4048
R/W 0 0xE001 404C
R/W 0 0xE001 4050
(Table 156), seven for the match
Reset value
0
0
0
0
0000
0
0
0
NA
Table 157.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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