Philips LPC213 Series User Manual page 106

Philips Semiconductors
Volume 1
10.3.11 UART1 Modem Status Register (U1MSR - 0xE001 0018), LPC2134/6/8
only
The U1MSR is a read-only register that provides status information on the modem input
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
affect on UART1 operation, they facilitate software implementation of modem signal
operations.
Table 101: UART1 Modem Status Register (U1MSR - address 0xE001 0018), LPC2134/6/8 only bit description
Bit Symbol Value Description
0 Delta CTS
0
1
1 Delta DSR
0
1
2 Trailing Edge RI
0
1
3 Delta DCD
0
1
4 CTS
5 DSR
6 RI
7 DCD
10.3.12 UART1 Scratch pad register (U1SCR - 0xE001 001C)
The U1SCR has no effect on the UART1 operation. This register can be written and/or
read at user's discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U1SCR has occurred.
Table 102: UART1 Scratch pad register (U1SCR - address 0xE001 0014) bit description
Bit Symbol
7:0 Pad
10.3.13 UART1 Transmit Enable Register (U1TER - 0xE001 0030)
LPC2131/2/4/6/8's U1TER enables implementation of software and hardware flow control.
When TXEn=1, UART1 transmitter will keep sending data as long as they are available.
As soon as TXEn becomes 0, UART1 transmittion will stop.
Table 103
User manual
Set upon state change of input CTS. Cleared on an U1MSR read.
No change detected on modem input, CTS.
State change detected on modem input, CTS.
Set upon state change of input DSR. Cleared on an U1MSR read.
No change detected on modem input, DSR.
State change detected on modem input, DSR.
Set upon low to high transition of input RI. Cleared on an U1MSR read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Set upon state change of input DCD. Cleared on an U1MSR read.
No change detected on modem input, DCD.
State change detected on modem input, DCD.
Clear To Send State. Complement of input signal CTS. This bit is connected
to U1MCR[1] in modem loopback mode.
Data Set Ready State. Complement of input signal DSR. This bit is connected
to U1MCR[0] in modem loopback mode.
Ring Indicator State. Complement of input RI. This bit is connected to
U1MCR[2] in modem loopback mode.
Data Carrier Detect State. Complement of input DCD. This bit is connected to
U1MCR[3] in modem loopback mode.
Description
A readable, writable byte.
describes how to use TXEn bit in order to achieve software flow control.
Rev. 01 — 24 June 2005
UM10120
Chapter 10: UART1
Reset value
0
0
0
0
0
0
0
0
Reset value
0x00
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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