Table of Contents
Advertisement
Philips Semiconductors
Volume 1
Table 155: Pulse Width Modulator (PWM) register map
Name
Description
PWMIR
PWM Interrupt Register. The PWMIR can be written to clear interrupts.
The PWMIR can be read to identify which of the possible interrupt
sources are pending.
PWMTCR PWM Timer Control Register. The PWMTCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the PWMTCR.
PWMTC
PWM Timer Counter. The 32-bit TC is incremented every PWMPR+1
cycles of PCLK. The PWMTC is controlled through the PWMTCR.
PWMPR
PWM Prescale Register. The PWMTC is incremented every PWMPR+1
cycles of PCLK.
PWMPC
PWM Prescale Counter. The 32-bit PC is a counter which is incremented
to the value stored in PR. When the value in PWMPR is reached, the
PWMTC is incremented. The PWMPC is observable and controllable
through the bus interface.
PWMMCR PWM Match Control Register. The PWMMCR is used to control if an
interrupt is generated and if the PWMTC is reset when a Match occurs.
PWMMR0 PWM Match Register 0. PWMMR0 can be enabled through PWMMCR to
reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate
an interrupt when it matches the PWMTC. In addition, a match between
PWMMR0 and the PWMTC sets all PWM outputs that are in single-edge
mode, and sets PWM1 if it is in double-edge mode.
PWMMR1 PWM Match Register 1. PWMMR1 can be enabled through PWMMCR to
reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate
an interrupt when it matches the PWMTC. In addition, a match between
PWMMR1 and the PWMTC clears PWM1 in either single-edge mode or
double-edge mode, and sets PWM2 if it is in double-edge mode.
PWMMR2 PWM Match Register 2. PWMMR2 can be enabled through PWMMCR to
reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate
an interrupt when it matches the PWMTC. In addition, a match between
PWMMR2 and the PWMTC clears PWM2 in either single-edge mode or
double-edge mode, and sets PWM3 if it is in double-edge mode.
PWMMR3 PWM Match Register 3. PWMMR3 can be enabled through PWMMCR to
reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate
an interrupt when it matches the PWMTC. In addition, a match between
PWMMR3 and the PWMTC clears PWM3 in either single-edge mode or
double-edge mode, and sets PWM4 if it is in double-edge mode.
PWMMR4 PWM Match Register 4. PWMMR4 can be enabled through PWMMCR to
reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate
an interrupt when it matches the PWMTC. In addition, a match between
PWMMR4 and the PWMTC clears PWM4 in either single-edge mode or
double-edge mode, and sets PWM5 if it is in double-edge mode.
PWMMR5 PWM Match Register 5. PWMMR5 can be enabled through PWMMCR to
reset the PWMTC, stop both the PWMTC and PWMPC, and/or generate
an interrupt when it matches the PWMTC. In addition, a match between
PWMMR5 and the PWMTC clears PWM5 in either single-edge mode or
double-edge mode, and sets PWM6 if it is in double-edge mode.
User manual
Rev. 01 — 24 June 2005
UM10120
Chapter 15: PWM
Access
Reset
Address
[1]
value
R/W
0
0xE001 4000
R/W
0
0xE001 4004
R/W
0
0xE001 4008
R/W
0
0xE001 400C
R/W
0
0xE001 4010
R/W
0
0xE001 4014
R/W
0
0xE001 4018
R/W
0
0xE001 401C
R/W
0
0xE001 4020
R/W
0
0xE001 4024
R/W
0
0xE001 4040
R/W
0
0xE001 4044
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
186
Advertisement
Table of Contents
