Philips LPC213 Series User Manual page 212

19.1 Features
19.2 Applications
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to "feed" (or reload) the watchdog within a predetermined
amount of time.
For interaction of the on-chip watchdog and other peripherals, especially the reset and
boot-up procedures, please read
19.3 Description
The watchdog consists of a divide by 4 fixed pre-scaler and a 32-bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum watchdog interval is (T
and the maximum watchdog interval is (T
watchdog should be used in the following manner:
When the Watchdog counter underflows, the program counter will start from 0x0000 0000
as in the case of external reset. The Watchdog Time-Out Flag (WDTOF) can be examined
to determine if the watchdog has caused the reset condition. The WDTOF flag must be
cleared by software.
User manual
UM10120
Chapter 19: Watchdog Timer
Rev. 01 — 24 June 2005
•
Internally resets chip if not periodically reloaded.
•
Debug mode.
•
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
•
Flag to indicate Watchdog reset.
•
Programmable 32-bit timer with internal pre-scaler.
•
Selectable time period from (T
T x 4.
PCLK
•
Set the watchdog timer constant reload value in WDTC register.
•
Setup mode in WDMOD register.
•
Start the watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
•
Watchdog should be fed again before the watchdog counter underflows to prevent
reset/interrupt.
Rev. 01 — 24 June 2005
x 256 x 4) to (T
PCLK PCLK
Section 3.9 "Reset" on page 35
32
x 2 x 4) in multiples of (T
PCLK
User manual
32
x 2 x 4) in multiples of
of this document.
x 256 x 4)
PCLK
x 4). The
PCLK
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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