Mitsubishi Electric Melsec Q Series Programming Manual page 183

3 MOTION DEDICATED PLC INSTRUCTION
CPU dedicated instruction transmission area shown in table below is
allocated as initial setting.
Table 3.1 Number of CPU dedicated instruction transmission area
Number of Multiple CPU modules
2
3
4
As shown in Table 3.2, each Motion dedicated PLC instruction uses a
certain number of blocks in the CPU dedicated instruction transmission area
until the "complete device" turns on by the PLC CPU after instruction
execution.
Table 3.2 Number of blocks used for Motion dedicated PLC instruction
Instructions
D(P).SFCS
D(P).SVST
D(P).CHGA
Ver.!
D(P).CHGAS QDS
D(P).CHGV
Ver.!
D(P).CHGVS QDS
D(P).CHGT
D(P).CHGT2 QDS
D(P).DDWR
D(P).DDRD
D(P).GINT
(Note): When the number of transmitted data is 4 words or less, number of blocks used is 1.
[Operation example]
Below is an example when 12 D(P).SVST instructions and 12 D(P).DDWR
instructions (5 word or more each) are executed simultaneously.
The number of blocks used is as follows;
12 D(P).SVST instructions
12 D(P).DDWR instructions
= 36 (Total blocks used)
Ver.!
: Refer to Section 1.3 for the software version that supports this function.
Number of CPU dedicated instruction transmission area for
Number of blocks used
1 block each +
2 blocks each
3 - 72
each target CPU
47 blocks
23 blocks
15 blocks
1
1
1
1
1
1
1
1
(Note)
2
(Note)
2
1