Mitsubishi Electric Melsec Q Series Programming Manual page 182

3 MOTION DEDICATED PLC INSTRUCTION
CPU shared memory address
(Decimal address)
30H(48)
31H(49)
32H(50)
33H(51)
206H(518)
207H(519)
208H(520)
20CH(524)
20DH(525)
(b) "Fixed at 0" area
The following area, which is used in Q173HCPU/Q172HCPU/
Q173CPU(N)/Q172CPU(N) is not used in Q173D(S)CPU/Q172D(S)CPU
and is therefore "Fixed at 0" for these processor.
The following interlocks are not used in new Q173D(S)CPU/Q172D(S)CPU
sequence program.
Fixed at 0 (To self CPU high speed interrupt accept flag from CPU1)
Fixed at 0 (To self CPU high speed interrupt accept flag from CPU2)
Fixed at 0 (To self CPU high speed interrupt accept flag from CPU3)
Fixed at 0 (To self CPU high speed interrupt accept flag from CPU4)
Fixed at 0 (Speed changing flag (Axis1 to 16))
Fixed at 0 (Speed changing flag (Axis17 to 32))
Fixed at 0 (Synchronous encoder current value changing flag (Axis1 to 12))
Fixed at 0 (Current value within 1cam shaft revolution changing flag (Axis1 to 16))
Fixed at 0 (Current value within 1cam shaft revolution changing flag (Axis17 to 32))
(2) CPU dedicated instruction transmission
(a) Outline operation of Motion Dedicated PLC Instruction
Motion dedicated PLC instruction is transmitted through the CPU dedicated
instruction transmission area set up in the system area on shared memory
at the Multiple CPU high speed transmission.
Outline operation for Motion dedicated PLC instruction is shown below.
OUT
<PLC CPU>
Motion dedicated instruction 1
Motion dedicated instruction 2
Description
(Q173HCPU/Q172HCPU/Q173CPU(N)/Q172CPU(N))
CPU dedicated instruction transmission area
1) Instruction execution
5) Complete device
Complete status
set (END processing)
3 - 71
<Motion CPU>
2) Instruction accept
3) Instruction process
(each 0.88ms)
Motion dedicated instruction 1
Motion dedicated instruction 2
4) Response data set