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10.100 TRAPA
Trap Exception
Handling
Format
TRAPA #imm
Description
This instruction starts trap exception handling. The values of (PC + 2) and SR are saved to SPC
and SSR, and 8-bit immediate data is stored in the TRA register (bits 9 to 2). The processor mode
is switched to privileged mode (the MD bit in SR is set to 1), and the BL bit and RB bit in SR are
set to 1. As a result, exception and interrupt requests are masked (not accepted), and the BANK1
registers (R0_BANK1 to R7_BANK1) are selected. Exception code 0x160 is written to the
EXPEVT register (bits 11 to 0). The program branches to address (VBR + H'00000100), indicated
by the sum of the VBR register contents and offset H'00000100.
Operation
TRAPA(int i) /* TRAPA #imm */
{
int imm;
imm=(0x000000FF & i);
TRA=imm<<2;
SSR=SR;
SPC=PC+2;
SR.MD=1;
SR.BL=1;
SR.RB=1;
EXPEVT=0x00000160;
PC=VBR+H'00000100;
}
TRAP Always
Summary of Operation
imm → TRA, PC+2 → SPC,
SR → SSR, 1 → SR.MD/
BL/RB, 0x160 → EXPEVT,
VBR+H'00000100 → PC
System Control Instruction
Instruction Code
11000011iiiiiiii 7
Rev. 2.0, 03/99, page 385 of 396
Execution
States
T Bit
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