Mitsubishi Electric Melsec iQ-R Series User Manual page 89

Hart-enabled analog-digital converter module
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HART device variables access flag
This signal turns on by turning off and on 'HART device variables access request' (Y3). While this signal is on, the following
buffer memory areas are not updated. Data inconsistency can be prevented by using this signal that turns on as an interlock
when data is read to the CPU module.
• 'CH1 HART field device status' (Un\G2080)
• 'CH1 HART extended field device status' (Un\G2081)
• 'CH1 HART device variable status primary value (PV), secondary value (SV)' (Un\G2082)
• 'CH1 HART device variable status tertiary value (TV), quaternary value (QV)' (Un\G2083)
• 'CH1 PV value' (Un\G2084, Un\G2085)
• 'CH1 SV value' (Un\G2086, Un\G2087)
• 'CH1 TV value' (Un\G2088, Un\G2089)
• 'CH1 QV value' (Un\G2090, Un\G2091)
This signal turns off and the update of the buffer memory restarts when 'HART device variables access request' (Y3) is turned
on and off.
'HART device variables access
request' (Y3)
OFF
'HART device variables access
OFF
flag' (X3)
Stored value in the target
buffer memory area
Performed by the A/D converter module
Performed by a program
■Device number
The following shows the device number of this input signal.
Signal name
HART device variables access flag
ON
ON
Previous value
CH1
CH2
X3
OFF
OFF
Refreshed value
CH3
CH4
CH5
CH6
Appendix 2 I/O Signals
A
CH7
CH8
APPX
87

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