Mitsubishi Electric Melsec iQ-R Series User Manual page 142

Hart-enabled analog-digital converter module
Hide thumbs Also See for Melsec iQ-R Series:
Table of Contents

Advertisement

CH1 HART device information (device function flags)
Availability of the functions of the used HART-enabled device is stored.
b15 b14 b13 b12 b11 b10 b9
0
0
0
0
0
(2)
(1) Device function flag
(2) b8 to b15 are fixed to 0.
When each bit of bit 0 to bit 7 is turned on, a HART-enabled device supports the following functions.
Target bit
Supported functions
bit0
Multi-sensor field device
bit1
EEPROM Control
bit2
Protocol bridge device
bit3
IEEE 802.15.4 2.4GHz DSSS with O-QPSK modulation
bit4
Not used
bit5
Not used
bit6
C8psk capable field device
bit7
C8psk in Multi-drop only
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH HART device information (device function
flags)
APPX
140
Appendix 3 Buffer Memory Areas
b8
b7
b6
b5
b4
0
0
0
CH1
2534
b3
b2
b1
b0
(1)
Description
The used HART-enabled device can execute multiple measurements in one
device. (For example, flow rate and concentration can be measured.)
The used HART-enabled device requires EEPROM Control. For details,
refer to the manual of the used HART-enabled device.
The used HART-enabled device can connect one network with another
network.
The used HART-enabled device supports a wireless HART communication.
The used HART-enabled device supports coherent 8-way phase-shift
keying (C8psk) protocol aside from FSK HART protocol. The A/D converter
module does not support C8psk.
The used HART-enabled device supports coherent 8-way phase-shift
keying (C8psk) protocol in the Multi-drop mode only. The A/D converter
module does not support the Multi-drop mode.
CH2
CH3
CH4
2634
2734
2834
CH5
CH6
CH7
2934
3034
3134
CH8
3234

Advertisement

Table of Contents
loading

Table of Contents