Mitsubishi Electric Melsec iQ-R Series User Manual page 137

HART command answer channel
A channel number executing a HART command is stored. The following information is stored.
b15 b14 b13 b12 b11 b10 b9
(2)
(1) A channel number executing a HART command is stored.
• 1: CH1
• 2: CH2
• 3: CH3
• 4: CH4
• 5: CH5
• 6: CH6
• 7: CH7
• 8: CH8
(2) Error information when a communication failure occurs with a HART-enabled device is stored.
• 0: No error
• 1: Timeout of a HART device answer
• 2: The number of retries reaches the maximum number of retries.
• 3: HART communication of the target channel is disabled.
• When 'HART command request flag' (Un\G2200) is set to No request (0), this area is cleared to 0.
• When Command execution error (1) is stored in bit 15 of 'HART command answer flag' (Un\G2344), 0 remains stored in
this area.
■Actions to be taken when error information is acquired
When error information 2 or 3 is stored in bit 8 to bit 15, check that the bit of the target channel is on in 'HART communication
enable/disable setting' (Un\G2074) and 'HART scan list' (Un\G2076). When the bit is on normally, check that the HART
command settings configured in the following buffer memory areas are correct by referring to the manual of the used HART-
enabled device.
• 'HART command request channel' (Un\G2201)
• 'HART command request code' (Un\G2202)
• 'HART command request data size' (Un\G2203)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART command answer channel
HART command answer code
A HART command executed is stored. When 'HART command request flag' (Un\G2200) is set to No request (0), this area is
cleared to 0. When Command execution error (1) is stored in bit 15 of 'HART command answer flag' (Un\G2344), 0 remains
stored in this area.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART command answer code
b8 b7 b6 b5 b4 b3 b2
(1)
CH1 CH2
2345
CH1 CH2
2346
b1 b0
CH3 CH4 CH5
CH3 CH4 CH5
CH6 CH7 CH8
CH6 CH7 CH8
APPX
Appendix 3 Buffer Memory Areas
A
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