Mitsubishi Electric Melsec iQ-R Series User Manual page 127

HART communication enable/disable setting monitor
Enable/disable status of the HART communication is stored for each channel.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0 0 0
(2)
(1) 0: Disable, 1: Enable
(2) b8 to b15 are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART communication enable/disable setting
monitor
HART scan list
The detection status of the HART-enabled device is stored for each channel.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0 0 0
(2)
(1) 0: Undetected, 1: Detected
(2) b8 to b15 are fixed to 0.
• When a HART-enabled device is detected in a channel where the HART communication is enabled, Detected (1) is stored
in the bit corresponding to the channel.
• When the HART communication is disconnected, Undetected (0) is stored in the bit corresponding to the channel.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART scan list
HART current cycle time
The current HART cycle time is stored in increments of 10ms. The stored value is updated as the HART cycle time elapses.
Ex.
When the stored value is 100, the current HART cycle time is 1s (100  10ms).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
HART current cycle time
■Resetting the stored value
The stored value is reset when:
• The power is turned off.
• The CPU module is reset.
• The HART communication functions of all channels are disabled.
b8 b7 b6 b5 b4 b3 b2
0 CH8 CH7 CH6 CH5 CH4 CH3 CH2
(1)
CH1 CH2
2075
b8 b7 b6 b5 b4 b3 b2
0 CH8 CH7 CH6 CH5 CH4 CH3 CH2
(1)
CH1 CH2
2076
CH1 CH2
2077
b1 b0
CH1
CH3 CH4 CH5
b1 b0
CH1
CH3 CH4 CH5
CH3 CH4 CH5
CH6 CH7 CH8
CH6 CH7 CH8
CH6 CH7 CH8
APPX
Appendix 3 Buffer Memory Areas
A
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