Mitsubishi Electric Melsec iQ-R Series User Manual page 146

CH1 HART device information (PV transfer function)
The information on a function used to convert the PV value to the current value by the used HART-enabled device is stored.
For details on the stored values, refer to the standard specifications of the HART or the manual of the used HART-enabled
device.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH HART device information (PV transfer
function)
CH1 HART device information (PV engineering unit)
An engineering unit of the PV value of the used HART-enabled device is stored. A value defined by the standard
specifications of the HART is stored for each engineering unit. For details on the stored values, refer to the standard
specifications of the HART or the manual of the used HART-enabled device.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH HART device information (PV engineering
unit)
CH1 HART device information (SV engineering unit)
An engineering unit of the SV value of the used HART-enabled device is stored. A value defined by the standard
specifications of the HART is stored for each engineering unit. For details on the stored values, refer to the standard
specifications of the HART or the manual of the used HART-enabled device.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH HART device information (SV engineering
unit)
CH1 HART device information (TV engineering unit)
An engineering unit of the TV value of the used HART-enabled device is stored. A value defined by the standard
specifications of the HART is stored for each engineering unit. For details on the stored values, refer to the standard
specifications of the HART or the manual of the used HART-enabled device.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH HART device information (TV engineering
unit)
APPX
144
Appendix 3 Buffer Memory Areas
CH1 CH2 CH3
2566 2666 2766
CH1 CH2 CH3
2567 2667 2767
CH1 CH2 CH3
2568 2668 2768
CH1 CH2 CH3
2569 2669 2769
CH4 CH5 CH6
2866 2966 3066
CH4 CH5 CH6
2867 2967 3067
CH4 CH5 CH6
2868 2968 3068
CH4 CH5 CH6
2869 2969 3069
CH7 CH8
3166 3266
CH7 CH8
3167 3267
CH7 CH8
3168 3268
CH7 CH8
3169 3269